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GET /api/1.1/patches/2227756/?format=api
{ "id": 2227756, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227756/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com>", "date": "2026-04-24T07:57:37", "name": "[v4,4/7] PCI/MSI: Introduce __pcim_enable_msix_range()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a549d7aef8bd9d45a7ebc9cf37ce402397aa2feb", "submitter": { "id": 66993, "url": "http://patchwork.ozlabs.org/api/1.1/people/66993/?format=api", "name": "Shawn Lin", "email": "shawn.lin@rock-chips.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com/mbox/", "series": [ { "id": 501313, "url": "http://patchwork.ozlabs.org/api/1.1/series/501313/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501313", "date": "2026-04-24T07:57:33", "name": "Add Devres managed IRQ vectors allocation", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/501313/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227756/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227756/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53123-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=kV+ImfAB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-53123-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=\"kV+ImfAB\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=117.135.214.68", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=rock-chips.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g25Q729pRz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 18:16:15 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 23E0C3003BFD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 08:16:13 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 26F3D31079B;\n\tFri, 24 Apr 2026 08:16:11 +0000 (UTC)", "from mail-m21468.qiye.163.com (mail-m21468.qiye.163.com\n [117.135.214.68])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 058511F3BAC\n\tfor <linux-pci@vger.kernel.org>; Fri, 24 Apr 2026 08:16:08 +0000 (UTC)", "from localhost.localdomain (unknown [61.154.14.86])\n\tby smtp.qiye.163.com (Hmail) with ESMTP id 3c0205330;\n\tFri, 24 Apr 2026 15:58:53 +0800 (GMT+08:00)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777018571; cv=none;\n b=bHb3XIPOn0RxA4wECcZIgaPVw1f42ms+OEnTsWCtYrrdK60kMrOvFiT7OlVjFkwjqq4ioM59AYHVULWS5Xu6htobGBrcPo0dOP+jBxvs+YvsTeDnvteewTLkPde9yaukllSfRw3I++v1230gyYZa/uWgP4mYKyQd/d9Eg+18VRM=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777018571; c=relaxed/simple;\n\tbh=/WLmShfTe09UWkzARJLXYwpdw4V4ubJdJX8bzAimaTs=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References;\n b=AqiGov9TMud95nRq4U9unA+4/UtlRcdMFHDNaAROJJhne9ncEY8pElLIEMf7iFhIy/cQdQVLmTZt6u1nEURRr0Wwn3hFUZn8PhYQX4na0HahzpfIQ0fj0NAJV9BDVTqaFVBAZ1Ps16kunSaUuFRXDquDp0i2xhFfZ8rtxFWYjTc=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com;\n spf=pass smtp.mailfrom=rock-chips.com;\n dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=kV+ImfAB; arc=none smtp.client-ip=117.135.214.68", "From": "Shawn Lin <shawn.lin@rock-chips.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>", "Cc": "Nirmal Patel <nirmal.patel@linux.intel.com>,\n\tJonathan Derrick <jonathan.derrick@linux.dev>,\n\tKurt Schwemmer <kurt.schwemmer@microsemi.com>,\n\tLogan Gunthorpe <logang@deltatee.com>,\n\tPhilipp Stanner <phasta@kernel.org>,\n\tlinux-pci@vger.kernel.org,\n\tShawn Lin <shawn.lin@rock-chips.com>", "Subject": "[PATCH v4 4/7] PCI/MSI: Introduce __pcim_enable_msix_range()", "Date": "Fri, 24 Apr 2026 15:57:37 +0800", "Message-Id": "<1777017460-243543-5-git-send-email-shawn.lin@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>", "References": "<1777017460-243543-1-git-send-email-shawn.lin@rock-chips.com>", "X-HM-Tid": "0a9dbe7fb4aa09cckunm66d640875eb88", "X-HM-MType": "1", "X-HM-Spam-Status": "e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlCTUgZVkpMSkgdTRpLSkNNSlYVFA\n\tkWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU\n\t9PT0tVSktLVUtZBg++", "DKIM-Signature": "a=rsa-sha256;\n\tb=kV+ImfABC4r83H00yEIwQYw9ay6IYjhyT4tdOY1E74JcBwMONHI8S6gqUOMRNEFaXfjVYeedD9OWdTLVDBhym6jj1dV3j2GQDampBipoWhgckyi9DG3YNpMMpnWKp5ABmM5S6WQIZnzIPpU1dCbFeKLFIPZ/j19xeF8ZambYmbI=;\n c=relaxed/relaxed; s=default; d=rock-chips.com; v=1;\n\tbh=tUGBWeaNM4DC0fKMSuIkB31wERPflv0/PrY+shHbQpg=;\n\th=date:mime-version:subject:message-id:from;", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>" }, "content": "Introduce __pcim_enable_msix_range(), a devres-managed variant of\n__pci_enable_msix_range(). Similar to the previously added MSI variant,\nthis function provides automatic cleanup of MSI-X interrupts via devres,\nreducing the risk of resource leaks and simplifying driver error handling.\n\nThis function is particularly useful for drivers that already use\npcim_enable_device() and want consistent devres management for all\nPCI resources, including MSI-X interrupts.\n\nDrivers can replace calls to __pci_enable_msix_range() with\n__pcim_enable_msix_range() to benefit from automatic cleanup without\nchanging their core logic. The flags parameter (e.g., PCI_IRQ_VIRTUAL)\nis fully supported and passed through to the underlying functions.\n\nThis completes the set of devres-managed MSI/MSI-X allocation functions,\nproviding a consistent API for driver authors who prefer automatic\nresource management.\n\nSigned-off-by: Shawn Lin <shawn.lin@rock-chips.com>\n---\n\nChanges in v4: None\nChanges in v3: None\nChanges in v2: None\n\n drivers/pci/msi/msi.c | 22 ++++++++++++++++++++++\n drivers/pci/msi/msi.h | 2 ++\n 2 files changed, 24 insertions(+)", "diff": "diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c\nindex 0aaff57..8fdf40d 100644\n--- a/drivers/pci/msi/msi.c\n+++ b/drivers/pci/msi/msi.c\n@@ -930,6 +930,28 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,\n \treturn pci_msix_range_init(dev, entries, minvec, nvec, hwsize, affd);\n }\n \n+int __pcim_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,\n+\t\t\t int minvec, int maxvec, struct irq_affinity *affd,\n+\t\t\t int flags)\n+{\n+\tint hwsize, nvec, rc;\n+\n+\thwsize = pci_msix_range_alloc(dev, entries, minvec,\n+\t\t\t\t maxvec, flags, &nvec);\n+\tif (hwsize < 0)\n+\t\treturn hwsize;\n+\n+\trc = msi_setup_device_data(&dev->dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = devm_add_action(&dev->dev, pcim_msi_release, dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn pci_msix_range_init(dev, entries, minvec, nvec, hwsize, affd);\n+}\n+\n void __pci_restore_msix_state(struct pci_dev *dev)\n {\n \tstruct msi_desc *entry;\ndiff --git a/drivers/pci/msi/msi.h b/drivers/pci/msi/msi.h\nindex 81c6b099..e6364a8 100644\n--- a/drivers/pci/msi/msi.h\n+++ b/drivers/pci/msi/msi.h\n@@ -97,6 +97,8 @@ int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct i\n int __pcim_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec, struct irq_affinity *affd);\n int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec,\n \t\t\t int maxvec, struct irq_affinity *affd, int flags);\n+int __pcim_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int minvec,\n+\t\t\t int maxvec, struct irq_affinity *affd, int flags);\n void __pci_restore_msi_state(struct pci_dev *dev);\n void __pci_restore_msix_state(struct pci_dev *dev);\n \n", "prefixes": [ "v4", "4/7" ] }