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GET /api/1.1/patches/2227675/?format=api
{ "id": 2227675, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227675/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-38-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260424043014.46305-38-richard.henderson@linaro.org>", "date": "2026-04-24T04:30:11", "name": "[v2,37/40] target/arm: Implement LUTI2, LUTI4 for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a23dec5981a2b0ac271366400b4cee14fe28b53c", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.1/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260424043014.46305-38-richard.henderson@linaro.org/mbox/", "series": [ { "id": 501300, "url": "http://patchwork.ozlabs.org/api/1.1/series/501300/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501300", "date": "2026-04-24T04:29:37", "name": "target/arm: Implement FEAT_FP8", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501300/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227675/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227675/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fOIpUg+m;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g20TW23psz1yDD\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 24 Apr 2026 14:33:51 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wG8Dr-0003rd-Mu; Fri, 24 Apr 2026 00:32:59 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8Dk-0003LX-4a\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:52 -0400", "from mail-oa1-x32.google.com ([2001:4860:4864:20::32])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wG8Dg-0003qC-3U\n for qemu-devel@nongnu.org; Fri, 24 Apr 2026 00:32:50 -0400", "by mail-oa1-x32.google.com with SMTP id\n 586e51a60fabf-40efc77933fso4920468fac.3\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 21:32:47 -0700 (PDT)", "from stoup.. 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"<20260424043014.46305-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2001:4860:4864:20::32;\n envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-defs.h | 5 ++++\n target/arm/tcg/translate-a64.c | 38 +++++++++++++++++++++++++\n target/arm/tcg/vec_helper.c | 52 ++++++++++++++++++++++++++++++++++\n target/arm/tcg/a64.decode | 6 ++++\n 4 files changed, 101 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h\nindex 5a10a9fba3..0db29d13d4 100644\n--- a/target/arm/tcg/helper-defs.h\n+++ b/target/arm/tcg/helper-defs.h\n@@ -1122,3 +1122,8 @@ DEF_HELPER_FLAGS_4(sme2_luti4_2s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_4(sme2_luti4_4h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_4s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_4(gvec_luti2_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\n+DEF_HELPER_FLAGS_4(gvec_luti2_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\n+DEF_HELPER_FLAGS_4(gvec_luti4_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\n+DEF_HELPER_FLAGS_4(gvec_luti4_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 6013226266..165dfa4484 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -5404,6 +5404,44 @@ static bool trans_TBL_TBX(DisasContext *s, arg_TBL_TBX *a)\n return true;\n }\n \n+static bool do_lut_1(DisasContext *s, arg_rrx_e *a, gen_helper_gvec_3 *fn)\n+{\n+ if (fp_access_check(s)) {\n+ gen_gvec_op3_ool(s, true, a->rd, a->rn, a->rm, a->idx, fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(LUTI2_1b, aa64_lut, do_lut_1, a, gen_helper_gvec_luti2_b)\n+TRANS_FEAT(LUTI2_1h, aa64_lut, do_lut_1, a, gen_helper_gvec_luti2_h)\n+TRANS_FEAT(LUTI4_1b, aa64_lut, do_lut_1, a, gen_helper_gvec_luti4_b)\n+\n+static bool trans_LUTI4_2h(DisasContext *s, arg_rrx_e *a)\n+{\n+ if (!dc_isar_feature(aa64_lut, s)) {\n+ return false;\n+ }\n+ if (fp_access_check(s)) {\n+ /*\n+ * (Ab)use preg_tmp to merge two disjoint 128-bit quantities\n+ * into a sequential 256-bit table.\n+ */\n+ QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, vfp.preg_tmp) < 32);\n+ unsigned tmp_ofs = offsetof(CPUARMState, vfp.preg_tmp);\n+ unsigned rn0_ofs = vec_full_reg_offset(s, a->rn);\n+ unsigned rn1_ofs = vec_full_reg_offset(s, (a->rn + 1) % 32);\n+\n+ tcg_gen_gvec_mov(MO_64, tmp_ofs, rn0_ofs, 16, 16);\n+ tcg_gen_gvec_mov(MO_64, tmp_ofs + 16, rn1_ofs, 16, 16);\n+\n+ tcg_gen_gvec_3_ool(vec_full_reg_offset(s, a->rd), tmp_ofs,\n+ vec_full_reg_offset(s, a->rm),\n+ 16, vec_full_reg_size(s),\n+ a->idx, gen_helper_gvec_luti4_h);\n+ }\n+ return true;\n+}\n+\n typedef int simd_permute_idx_fn(int i, int part, int elements);\n \n static bool do_simd_permute(DisasContext *s, arg_qrrr_e *a,\ndiff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex 91e98d28ae..16032bb6f5 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -3348,3 +3348,55 @@ DO_SME2_LUT(4,4,h, 2)\n DO_SME2_LUT(4,4,s, 4)\n \n #undef DO_SME2_LUT\n+\n+void HELPER(gvec_luti2_b)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 8;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_b(&scratch, vm, vn, elements, ibase, 0, 2, 8, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_luti2_h)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 16;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_h(&scratch, vm, vn, elements, ibase, 0, 2, 16, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_luti4_b)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 8;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_b(&scratch, vm, vn, elements, ibase, 0, 4, 8, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_luti4_h)(void *vd, void *vn, void *vm, uint32_t desc)\n+{\n+ unsigned part = simd_data(desc);\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned elements = vl / 16;\n+ unsigned ibase = elements * part;\n+ ARMVectorReg scratch;\n+\n+ do_lut_h(&scratch, vm, vn, elements, ibase, 0, 2, 16, 1);\n+ memcpy(vd, &scratch, vl);\n+ clear_tail(vd, vl, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex a9cf259b9b..6aea3ce89f 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1344,6 +1344,12 @@ EXT_q 0110 1110 00 0 rm:5 0 imm:4 0 rn:5 rd:5\n \n TBL_TBX 0 q:1 00 1110 000 rm:5 0 len:2 tbx:1 00 rn:5 rd:5\n \n+LUTI2_1b 0100 1110 100 rm:5 0 idx:2 100 rn:5 rd:5 &rrx_e esz=0\n+LUTI2_1h 0100 1110 110 rm:5 0 idx:3 00 rn:5 rd:5 &rrx_e esz=1\n+\n+LUTI4_1b 0100 1110 010 rm:5 0 idx:1 1000 rn:5 rd:5 &rrx_e esz=0\n+LUTI4_2h 0100 1110 010 rm:5 0 idx:2 100 rn:5 rd:5 &rrx_e esz=1\n+\n # Advanced SIMD Permute\n \n UZP1 0.00 1110 .. 0 ..... 0 001 10 ..... ..... @qrrr_e\n", "prefixes": [ "v2", "37/40" ] }