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{
    "id": 2227386,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227386/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20260423145705.545552-5-mukesh.savaliya@oss.qualcomm.com/",
    "project": {
        "id": 35,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/35/?format=api",
        "name": "Linux I2C development",
        "link_name": "linux-i2c",
        "list_id": "linux-i2c.vger.kernel.org",
        "list_email": "linux-i2c@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260423145705.545552-5-mukesh.savaliya@oss.qualcomm.com>",
    "date": "2026-04-23T14:55:51",
    "name": "[v7,4/4] i2c: qcom-geni: Support multi-owner controllers in GPI mode",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "70980174bfae9f9afcf0c6080caf6c264a537bba",
    "submitter": {
        "id": 91179,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/91179/?format=api",
        "name": "Mukesh Kumar Savaliya",
        "email": "mukesh.savaliya@oss.qualcomm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/patch/20260423145705.545552-5-mukesh.savaliya@oss.qualcomm.com/mbox/",
    "series": [
        {
            "id": 501206,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501206/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/list/?series=501206",
            "date": "2026-04-23T14:55:48",
            "name": "Enable multi-owner I2C support for QCOM GENI controllers",
            "version": 7,
            "mbox": "http://patchwork.ozlabs.org/series/501206/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2227386/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2227386/checks/",
    "tags": {},
    "headers": {
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        "From": "Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>",
        "To": "viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org,\n        krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,\n        Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org,\n        dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com,\n        quic_jseerapu@quicinc.com, agross@kernel.org,\n        linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org,\n        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n        dmaengine@vger.kernel.org",
        "Cc": "krzysztof.kozlowski@oss.qualcomm.com,\n bartosz.golaszewski@oss.qualcomm.com,\n        bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com,\n        Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>",
        "Subject": "[PATCH v7 4/4] i2c: qcom-geni: Support multi-owner controllers in GPI\n mode",
        "Date": "Thu, 23 Apr 2026 20:25:51 +0530",
        "Message-ID": "<20260423145705.545552-5-mukesh.savaliya@oss.qualcomm.com>",
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    },
    "content": "Some platforms use a QUP-based I2C controller in a configuration where the\ncontroller is shared with another system processor. In this setup the\noperating system must not assume exclusive ownership of the controller or\nits associated pins.\n\nAdd support for enabling multi-owner operation when DeviceTree specifies\nqcom,qup-multi-owner. When enabled, mark the underlying serial engine as\nshared so the common GENI resource handling avoids selecting the \"sleep\"\npinctrl state, which could disrupt transfers initiated by the other\nprocessor.\n\nFor GPI mode transfers, request lock/unlock TRE sequencing from the GPI\ndriver by setting a single lock_action selector per message, emitting lock\nbefore the first message and unlock after the last message (handling the\nsingle-message case as well). This serializes access to the shared\ncontroller without requiring message-position flags to be passed into the\nDMA engine layer.\n\nSigned-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>\n---\n drivers/i2c/busses/i2c-qcom-geni.c | 22 +++++++++++++++++++++-\n 1 file changed, 21 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c\nindex ae609bdd2ec4..a396ddc7d8f4 100644\n--- a/drivers/i2c/busses/i2c-qcom-geni.c\n+++ b/drivers/i2c/busses/i2c-qcom-geni.c\n@@ -815,6 +815,14 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], i\n \t\tif (i < num - 1)\n \t\t\tperipheral.stretch = 1;\n \n+\t\tperipheral.lock_action = GPI_LOCK_NONE;\n+\t\tif (gi2c->se.multi_owner) {\n+\t\t\tif (i == 0)\n+\t\t\t\tperipheral.lock_action = GPI_LOCK_ACQUIRE;\n+\t\t\telse if (i == num - 1)\n+\t\t\t\tperipheral.lock_action = GPI_LOCK_RELEASE;\n+\t\t}\n+\n \t\tperipheral.addr = msgs[i].addr;\n \t\tif (i > 0 && (!(msgs[i].flags & I2C_M_RD)))\n \t\t\tperipheral.multi_msg = false;\n@@ -1014,6 +1022,11 @@ static int geni_i2c_probe(struct platform_device *pdev)\n \t\tgi2c->clk_freq_out = I2C_MAX_STANDARD_MODE_FREQ;\n \t}\n \n+\tif (of_property_read_bool(pdev->dev.of_node, \"qcom,qup-multi-owner\")) {\n+\t\tgi2c->se.multi_owner = true;\n+\t\tdev_dbg(&pdev->dev, \"I2C controller is shared with another system processor\\n\");\n+\t}\n+\n \tif (has_acpi_companion(dev))\n \t\tACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));\n \n@@ -1089,7 +1102,9 @@ static int geni_i2c_probe(struct platform_device *pdev)\n \t}\n \n \tif (fifo_disable) {\n-\t\t/* FIFO is disabled, so we can only use GPI DMA */\n+\t\t/* FIFO is disabled, so we can only use GPI DMA.\n+\t\t * SE can be shared in GSI mode between subsystems, each SS owns a GPII.\n+\t\t */\n \t\tgi2c->gpi_mode = true;\n \t\tret = setup_gpi_dma(gi2c);\n \t\tif (ret)\n@@ -1098,6 +1113,11 @@ static int geni_i2c_probe(struct platform_device *pdev)\n \t\tdev_dbg(dev, \"Using GPI DMA mode for I2C\\n\");\n \t} else {\n \t\tgi2c->gpi_mode = false;\n+\n+\t\tif (gi2c->se.multi_owner)\n+\t\t\treturn dev_err_probe(dev, -EINVAL,\n+\t\t\t\t\t     \"I2C sharing not supported in non GSI mode\\n\");\n+\n \t\ttx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);\n \n \t\t/* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */\n",
    "prefixes": [
        "v7",
        "4/4"
    ]
}