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GET /api/1.1/patches/2227227/?format=api
{ "id": 2227227, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227227/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-23-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260423100229.2941820-23-peter.maydell@linaro.org>", "date": "2026-04-23T10:01:52", "name": "[PULL,22/59] target/arm/tcg/translate.c: extract aarch64_translate_code()", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "76c917bb08a35a2c1252d4ae6da796afbba7c2fc", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-23-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501172, "url": "http://patchwork.ozlabs.org/api/1.1/series/501172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172", "date": "2026-04-23T10:01:35", "name": "[PULL,01/59] target/arm/tcg: increase cache level for cpu=max", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501172/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227227/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227227/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bJg3GUjH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Wwc70Ggz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 20:07:12 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFqtg-0006RG-08; Thu, 23 Apr 2026 06:03:00 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqte-0006Qq-Qr\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:58 -0400", "from mail-wm1-x333.google.com ([2a00:1450:4864:20::333])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqtd-00025U-4H\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:58 -0400", "by mail-wm1-x333.google.com with SMTP id\n 5b1f17b1804b1-4896c22fcbaso37566585e9.0\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 03:02:56 -0700 (PDT)", "from lanath.. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::333;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n\nThis allows to get rid of TARGET_AARCH64, and helps with next patch\nwhich will define at runtime tcg address type, by adding a second entry\npoint in a different source file.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\nMessage-id: 20260407222208.271838-14-pierrick.bouvier@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/internals.h | 2 ++\n target/arm/tcg/stubs32.c | 7 +++++++\n target/arm/tcg/translate-a64.c | 9 +++++++++\n target/arm/tcg/translate.c | 19 +++++++++----------\n 4 files changed, 27 insertions(+), 10 deletions(-)", "diff": "diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 6b16f1a560..af5e9a1acf 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);\n \n void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);\n void arm_translate_init(void);\n+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n+ int *max_insns, vaddr pc, void *host_pc);\n void arm_translate_code(CPUState *cs, TranslationBlock *tb,\n int *max_insns, vaddr pc, void *host_pc);\n \ndiff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\nindex c5a0bc61f4..3945dc49e5 100644\n--- a/target/arm/tcg/stubs32.c\n+++ b/target/arm/tcg/stubs32.c\n@@ -3,6 +3,7 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"target/arm/internals.h\"\n #include \"target/arm/tcg/translate.h\"\n \n \n@@ -15,3 +16,9 @@ void a64_translate_init(void)\n {\n /* Don't initialize for 32 bits. Call site will be fixed later. */\n }\n+\n+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n+ int *max_insns, vaddr pc, void *host_pc)\n+{\n+ g_assert_not_reached();\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 35ad7530c4..7533a4d01b 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -18,6 +18,7 @@\n */\n #include \"qemu/osdep.h\"\n #include \"exec/target_page.h\"\n+#include \"exec/translator.h\"\n #include \"helper-a64.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n@@ -10949,3 +10950,11 @@ const TranslatorOps aarch64_translator_ops = {\n .translate_insn = aarch64_tr_translate_insn,\n .tb_stop = aarch64_tr_tb_stop,\n };\n+\n+void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n+ int *max_insns, vaddr pc, void *host_pc)\n+{\n+ DisasContext dc = {};\n+ translator_loop(cpu, tb, max_insns, pc, host_pc,\n+ &aarch64_translator_ops, &dc.base);\n+}\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 204f965799..9ab926b118 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -28,6 +28,7 @@\n #include \"semihosting/semihost.h\"\n #include \"cpregs.h\"\n #include \"exec/target_page.h\"\n+#include \"exec/translator.h\"\n #include \"helper.h\"\n #include \"helper-mve.h\"\n \n@@ -6878,18 +6879,16 @@ static const TranslatorOps thumb_translator_ops = {\n void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n int *max_insns, vaddr pc, void *host_pc)\n {\n- DisasContext dc = { };\n- const TranslatorOps *ops = &arm_translator_ops;\n CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n \n- if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n- ops = &thumb_translator_ops;\n- }\n-#ifdef TARGET_AARCH64\n if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n- ops = &aarch64_translator_ops;\n+ aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n+ } else {\n+ DisasContext dc = { };\n+ translator_loop(cpu, tb, max_insns, pc, host_pc,\n+ (EX_TBFLAG_AM32(tb_flags, THUMB)\n+ ? &thumb_translator_ops\n+ : &arm_translator_ops),\n+ &dc.base);\n }\n-#endif\n-\n- translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);\n }\n", "prefixes": [ "PULL", "22/59" ] }