Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2227204/?format=api
{ "id": 2227204, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227204/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-10-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260423100229.2941820-10-peter.maydell@linaro.org>", "date": "2026-04-23T10:01:39", "name": "[PULL,09/59] target/arm: Move OMAP CP15 register definitions to cpregs-omap.c", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "0ce3e78a3187614be2a16b5686ebaf26f2452490", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-10-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501172, "url": "http://patchwork.ozlabs.org/api/1.1/series/501172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172", "date": "2026-04-23T10:01:35", "name": "[PULL,01/59] target/arm/tcg: increase cache level for cpu=max", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501172/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227204/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227204/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=RZV/iMPR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1Wtf2Mshz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 20:05:30 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFqtY-0006MJ-Dv; Thu, 23 Apr 2026 06:02:52 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqtQ-0006Jq-Mg\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:45 -0400", "from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqtO-000201-Gg\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:44 -0400", "by mail-wm1-x32a.google.com with SMTP id\n 5b1f17b1804b1-4838c15e3cbso59717235e9.3\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 03:02:42 -0700 (PDT)", "from lanath.. (wildly.archaic.org.uk. [81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4e4eec9sm49323930f8f.34.2026.04.23.03.02.39\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 23 Apr 2026 03:02:40 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1776938561; x=1777543361; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=GE5heDTE24qeg7bs1UHIGmavXNoRi4sL8/ptSkR7ee0=;\n b=RZV/iMPR9TFjwRPnAfIFwe50fHcNM7UafybEXBQZtQDXa+TfoggmV4opUKzTAMPSje\n UeFtUOtsNc1IOW784sIsSsrch4MHXpM49hZIBrry9rrmCvSp5mbXmgFexqs6V53tpYqz\n J6rC6417uhokEQHSYqnEkDJaBHFhTcC7CIihJqHHoO4zWUXoPN4rmaCxx4ZDfxMsNDIp\n 638mtY2cANPBzA0eP6SCtkBvvOi/nSla6F3w8H73mGgvEuFaPK70RAODeiQQtTeudVLe\n ytgtSdTqoGcqy6vdoRJv8lIOQlIfn9eQ6vpcp/M3tD3OcrwGAd+zpXr9xo5qNlXLydao\n E6cw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776938561; x=1777543361;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=GE5heDTE24qeg7bs1UHIGmavXNoRi4sL8/ptSkR7ee0=;\n b=GJTMnwQ5AG4SHQ4N8s4kER6qjPiS52aNxruuCplAL6TEB0CJ8DinaCXdP8TCLwOPpE\n IYhqqCfJoIwcROIC5xFki5Dq1yndYwKkMu7S+Jf5VujG5wt9VQExI+3/1noWyq/6Bz8m\n J29WUtZuntJY/WTmyZ4CK8lN6QVQHfGJJmXQl2UT6Eb9IFdTEGqvPCwYpduDlQniSgP1\n oJGyNM/j+gcjSq50evP3WWjU+e8waiH7Idi8X14Jv57nCx9ss3EMtCdrHXg/NVTlonsE\n 3ngp3ACUR7pjycr9/aFLwnc15ATxPSrsvpq+xZ5BiGDip8/8Grk5JZPKnA4ibYGHSyRL\n z2iA==", "X-Gm-Message-State": "AOJu0YzMwjsD+bxTarNeRvZfLRay2vlyLy/wvj9yW4U96OD44s1rNfMQ\n H/KwoJ+6WCVdR2wQSBXu1VQCbs3bkg5JDOW/5eqW6PsY8PEtv9sgh6aHh6SwKlxmZCQtTIVMW5S\n o+6jo", "X-Gm-Gg": "AeBDiesZ5gyogi9naR95c2OJbQdBsYuwMXeFOYx9JSV5Lnq/qRrqn9CczhBIP9uJl8A\n LGP7YWi0BVqYouGKyj2dYmYMO4E9ol2EufwGVCrLA9PXYJlHhyQ3UXbO9Zw6L/iHDm5JOa1MmB6\n wSQrLeR8En01YmR1erxQCkYa0611AurdmJqOZVeYTfZkaFkdF0dEhVJV824wZZeajBpPmROOco4\n JoQ6N2U3GirtoFTr4RdI/QDUF/aLAUJo1K0wJTtGVe5UfeYfCQSCLC6CDHtQrLUm/F7eINvH3jV\n 049d0DGxcf5P8dwJJ4XrLPZ6vC2OjE1e0i/0RDbp54yAQDGBhfFWCI4THgQqXmHrSNlB3rf1Zyo\n 1RFJilnp671Bzgt1tUWE+E5tLddIAoqrzF2PJKdfdL6aaYSoyWQC+rITVYVlMdsbuINWRHsfWrN\n 8L2FhU7HbYO3euZegmtY7ClHvILoHkQJYguOQ9b0EATF02LCZvvz2uSn5NJjeDnUwKtmQj+uZr3\n SB148x/tIWk6nkfz++m6DyzHmbRFnW/afgOlqlH4eNHfk1F0zRS", "X-Received": "by 2002:a05:6000:2909:b0:43f:e22d:e624 with SMTP id\n ffacd0b85a97d-43fe3db3cb2mr38391922f8f.1.1776938560794;\n Thu, 23 Apr 2026 03:02:40 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 09/59] target/arm: Move OMAP CP15 register definitions to\n cpregs-omap.c", "Date": "Thu, 23 Apr 2026 11:01:39 +0100", "Message-ID": "<20260423100229.2941820-10-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260423100229.2941820-1-peter.maydell@linaro.org>", "References": "<20260423100229.2941820-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Alessandro Ratti <alessandro@0x65c.net>\n\nThe OMAP CP15 registers are only relevant to system-mode emulation\nof OMAP SoCs. Move them out of the monolithic helper.c into a\ndedicated file, following the pattern of cpregs-pmu.c and\ncpregs-gcs.c. This reduces the size of helper.c and compiles\nthe OMAP-specific code out of CONFIG_USER_ONLY builds.\n\nSuggested-by: Paolo Bonzini <pbonzini@redhat.com>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Alessandro Ratti <alessandro@0x65c.net>\nMessage-id: 20260405180826.729652-1-alessandro@0x65c.net\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpregs-omap-stub.c | 10 ++++\n target/arm/cpregs-omap.c | 88 +++++++++++++++++++++++++++++++++++\n target/arm/helper.c | 79 +------------------------------\n target/arm/internals.h | 2 +\n target/arm/meson.build | 2 +\n 5 files changed, 103 insertions(+), 78 deletions(-)\n create mode 100644 target/arm/cpregs-omap-stub.c\n create mode 100644 target/arm/cpregs-omap.c", "diff": "diff --git a/target/arm/cpregs-omap-stub.c b/target/arm/cpregs-omap-stub.c\nnew file mode 100644\nindex 0000000000..39c511205c\n--- /dev/null\n+++ b/target/arm/cpregs-omap-stub.c\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/cpu-qom.h\"\n+#include \"internals.h\"\n+\n+void define_omap_cp_regs(ARMCPU *cpu)\n+{\n+ g_assert_not_reached();\n+}\ndiff --git a/target/arm/cpregs-omap.c b/target/arm/cpregs-omap.c\nnew file mode 100644\nindex 0000000000..ac855baada\n--- /dev/null\n+++ b/target/arm/cpregs-omap.c\n@@ -0,0 +1,88 @@\n+/*\n+ * QEMU ARM OMAP CP15 register definitions\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"target/arm/cpu.h\"\n+#include \"target/arm/cpregs.h\"\n+#include \"target/arm/internals.h\"\n+\n+static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ env->cp15.c15_ticonfig = value & 0xe7;\n+ /* The OS_TYPE bit in this register changes the reported CPUID! */\n+ env->cp15.c0_cpuid = (value & (1 << 5)) ?\n+ ARM_CPUID_TI915T : ARM_CPUID_TI925T;\n+}\n+\n+static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ env->cp15.c15_threadid = value & 0xffff;\n+}\n+\n+static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /* Wait-for-interrupt (deprecated) */\n+ cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);\n+}\n+\n+static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,\n+ uint64_t value)\n+{\n+ /*\n+ * On OMAP there are registers indicating the max/min index of dcache lines\n+ * containing a dirty line; cache flush operations have to reset these.\n+ */\n+ env->cp15.c15_i_max = 0x000;\n+ env->cp15.c15_i_min = 0xff0;\n+}\n+\n+static const ARMCPRegInfo omap_cp_reginfo[] = {\n+ { .name = \"DFSR\", .cp = 15, .crn = 5, .crm = CP_ANY,\n+ .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,\n+ .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),\n+ .resetvalue = 0, },\n+ { .name = \"\", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW, .type = ARM_CP_NOP },\n+ { .name = \"TICONFIG\", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,\n+ .writefn = omap_ticonfig_write },\n+ { .name = \"IMAX\", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },\n+ { .name = \"IMIN\", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW, .resetvalue = 0xff0,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },\n+ { .name = \"THREADID\", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,\n+ .access = PL1_RW,\n+ .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,\n+ .writefn = omap_threadid_write },\n+ { .name = \"TI925T_STATUS\", .cp = 15, .crn = 15,\n+ .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,\n+ .type = ARM_CP_NO_RAW,\n+ .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },\n+ /*\n+ * TODO: Peripheral port remap register:\n+ * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller\n+ * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),\n+ * when MMU is off.\n+ */\n+ { .name = \"OMAP_CACHEMAINT\", .cp = 15, .crn = 7, .crm = CP_ANY,\n+ .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,\n+ .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,\n+ .writefn = omap_cachemaint_write },\n+ { .name = \"C9\", .cp = 15, .crn = 9,\n+ .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,\n+ .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },\n+};\n+\n+void define_omap_cp_regs(ARMCPU *cpu)\n+{\n+ define_arm_cp_regs(cpu, omap_cp_reginfo);\n+}\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7389f2988c..3ac88078aa 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -2900,83 +2900,6 @@ static const ARMCPRegInfo ttbcr2_reginfo = {\n },\n };\n \n-static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- env->cp15.c15_ticonfig = value & 0xe7;\n- /* The OS_TYPE bit in this register changes the reported CPUID! */\n- env->cp15.c0_cpuid = (value & (1 << 5)) ?\n- ARM_CPUID_TI915T : ARM_CPUID_TI925T;\n-}\n-\n-static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- env->cp15.c15_threadid = value & 0xffff;\n-}\n-\n-static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n-#ifdef CONFIG_USER_ONLY\n- g_assert_not_reached();\n-#else\n- /* Wait-for-interrupt (deprecated) */\n- cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT);\n-#endif\n-}\n-\n-static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,\n- uint64_t value)\n-{\n- /*\n- * On OMAP there are registers indicating the max/min index of dcache lines\n- * containing a dirty line; cache flush operations have to reset these.\n- */\n- env->cp15.c15_i_max = 0x000;\n- env->cp15.c15_i_min = 0xff0;\n-}\n-\n-static const ARMCPRegInfo omap_cp_reginfo[] = {\n- { .name = \"DFSR\", .cp = 15, .crn = 5, .crm = CP_ANY,\n- .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,\n- .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),\n- .resetvalue = 0, },\n- { .name = \"\", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW, .type = ARM_CP_NOP },\n- { .name = \"TICONFIG\", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,\n- .writefn = omap_ticonfig_write },\n- { .name = \"IMAX\", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },\n- { .name = \"IMIN\", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW, .resetvalue = 0xff0,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },\n- { .name = \"THREADID\", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,\n- .access = PL1_RW,\n- .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,\n- .writefn = omap_threadid_write },\n- { .name = \"TI925T_STATUS\", .cp = 15, .crn = 15,\n- .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,\n- .type = ARM_CP_NO_RAW,\n- .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },\n- /*\n- * TODO: Peripheral port remap register:\n- * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller\n- * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),\n- * when MMU is off.\n- */\n- { .name = \"OMAP_CACHEMAINT\", .cp = 15, .crn = 7, .crm = CP_ANY,\n- .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,\n- .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,\n- .writefn = omap_cachemaint_write },\n- { .name = \"C9\", .cp = 15, .crn = 9,\n- .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,\n- .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },\n-};\n-\n static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {\n /*\n * RAZ/WI the whole crn=15 space, when we don't have a more specific\n@@ -7043,7 +6966,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);\n }\n if (arm_feature(env, ARM_FEATURE_OMAPCP)) {\n- define_arm_cp_regs(cpu, omap_cp_reginfo);\n+ define_omap_cp_regs(cpu);\n }\n if (arm_feature(env, ARM_FEATURE_STRONGARM)) {\n define_arm_cp_regs(cpu, strongarm_cp_reginfo);\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 85980f0e69..6b16f1a560 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1799,6 +1799,8 @@ void define_at_insn_regs(ARMCPU *cpu);\n void define_pm_cpregs(ARMCPU *cpu);\n /* Add the cpreg definitions for GCS cpregs */\n void define_gcs_cpregs(ARMCPU *cpu);\n+/* Add the cpreg definitions for OMAP CP15 regs */\n+void define_omap_cp_regs(ARMCPU *cpu);\n \n /* Effective value of MDCR_EL2 */\n static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)\ndiff --git a/target/arm/meson.build b/target/arm/meson.build\nindex 6e0e504a40..192ac7c31e 100644\n--- a/target/arm/meson.build\n+++ b/target/arm/meson.build\n@@ -33,6 +33,7 @@ arm_user_ss.add(files(\n 'helper.c',\n 'vfp_fpscr.c',\n 'el2-stubs.c',\n+ 'cpregs-omap-stub.c',\n ))\n arm_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING',\n \t\t if_true: files('common-semi-target.c'))\n@@ -48,6 +49,7 @@ arm_common_system_ss.add(files(\n 'arm-powerctl.c',\n 'cortex-regs.c',\n 'cpregs-gcs.c',\n+ 'cpregs-omap.c',\n 'cpregs-pmu.c',\n 'cpu-irq.c',\n 'debug_helper.c',\n", "prefixes": [ "PULL", "09/59" ] }