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GET /api/1.1/patches/2227199/?format=api
{ "id": 2227199, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227199/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-26-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260423100229.2941820-26-peter.maydell@linaro.org>", "date": "2026-04-23T10:01:55", "name": "[PULL,25/59] target/arm/tcg/translate-a64.c: use translator_ldl_end instead of arm_ldl_code", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "9d04d37535c006cd91710b7d9ce569350d9368c7", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-26-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501172, "url": "http://patchwork.ozlabs.org/api/1.1/series/501172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172", "date": "2026-04-23T10:01:35", "name": "[PULL,01/59] target/arm/tcg: increase cache level for cpu=max", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501172/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227199/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227199/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=UYs9zrx0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1WtM0cvzz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 20:05:15 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFqu6-0006Ui-B6; Thu, 23 Apr 2026 06:03:34 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqti-0006Sl-9r\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:03:02 -0400", "from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqtg-00027A-OD\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:03:02 -0400", "by mail-wr1-x42e.google.com with SMTP id\n ffacd0b85a97d-43d77f60944so5190573f8f.3\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 03:03:00 -0700 (PDT)", "from lanath.. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42e;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n\nAllows to reduce scope of target/arm/tcg/arm_ldst.h to aarch32 only.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\nMessage-id: 20260407222208.271838-17-pierrick.bouvier@linaro.org\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/tcg/translate-a64.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex df2cbd66b3..48b5c57255 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -26,7 +26,6 @@\n #include \"translate-a64.h\"\n #include \"tcg/tcg-op.h\"\n #include \"qemu/log.h\"\n-#include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n #include \"cpregs.h\"\n \n@@ -10801,7 +10800,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n if (pc & 3) {\n /*\n * PC alignment fault. This has priority over the instruction abort\n- * that we would receive from a translation fault via arm_ldl_code.\n+ * that we would receive from a translation fault via translator_ldl_end.\n * This should only be possible after an indirect branch, at the\n * start of the TB.\n */\n@@ -10813,7 +10812,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n }\n \n s->pc_curr = pc;\n- insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);\n+ /* Code is always little-endian on Aarch64 */\n+ insn = translator_ldl_end(env, &s->base, pc, MO_LE);\n s->insn = insn;\n s->base.pc_next = pc + 4;\n \n", "prefixes": [ "PULL", "25/59" ] }