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GET /api/1.1/patches/2227176/?format=api
{ "id": 2227176, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2227176/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-7-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260423100229.2941820-7-peter.maydell@linaro.org>", "date": "2026-04-23T10:01:36", "name": "[PULL,06/59] hw/acpi: add cache hierarchy to pptt table", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "e4a023bab34cde77a4bb57cae678ab12ee39e69d", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260423100229.2941820-7-peter.maydell@linaro.org/mbox/", "series": [ { "id": 501172, "url": "http://patchwork.ozlabs.org/api/1.1/series/501172/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501172", "date": "2026-04-23T10:01:35", "name": "[PULL,01/59] target/arm/tcg: increase cache level for cpu=max", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501172/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227176/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227176/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=AemfDpnT;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g1WrL1YVdz1yGs\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 23 Apr 2026 20:03:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFqtW-0006LV-5B; Thu, 23 Apr 2026 06:02:51 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqtN-0006Iz-I6\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:41 -0400", "from mail-wm1-x336.google.com ([2a00:1450:4864:20::336])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wFqtL-0001yV-79\n for qemu-devel@nongnu.org; Thu, 23 Apr 2026 06:02:41 -0400", "by mail-wm1-x336.google.com with SMTP id\n 5b1f17b1804b1-48984d29fe3so61713995e9.0\n for <qemu-devel@nongnu.org>; Thu, 23 Apr 2026 03:02:38 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Alireza Sanaee <alireza.sanaee@huawei.com>\n\nAdd cache topology to PPTT table.\n\nSigned-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>\nReviewed-by: Gustavo Romero <gustavo.romero@linaro.org>\nMessage-id: 20260311160609.358-7-alireza.sanaee@huawei.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/acpi/aml-build.c | 200 +++++++++++++++++++++++++++++++++++++--\n hw/arm/virt-acpi-build.c | 8 +-\n include/hw/acpi/cpu.h | 10 ++\n 3 files changed, 209 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c\nindex b0ea8a5d5d..7edc8aed42 100644\n--- a/hw/acpi/aml-build.c\n+++ b/hw/acpi/aml-build.c\n@@ -34,6 +34,7 @@\n #include \"hw/pci/pci_bridge.h\"\n #include \"hw/acpi/acpi_aml_interface.h\"\n #include \"qemu/cutils.h\"\n+#include \"hw/core/cpu.h\"\n \n static GArray *build_alloc_array(void)\n {\n@@ -2150,6 +2151,108 @@ void build_spcr(GArray *table_data, BIOSLinker *linker,\n }\n acpi_table_end(linker, &table);\n }\n+\n+/*\n+ * ACPI spec, Revision 6.3\n+ * 5.2.29.2 Cache Type Structure (Type 1)\n+ */\n+static void build_cache_nodes(GArray *tbl, CPUCoreCaches *cache,\n+ uint32_t next_offset)\n+{\n+ const uint8_t node_length = 24;\n+ int start_len = tbl->len;\n+ int val;\n+\n+ build_append_byte(tbl, 1); /* Type 1 - cache */\n+ build_append_byte(tbl, node_length); /* Length */\n+ build_append_int_noprefix(tbl, 0, 2); /* Reserved */\n+ build_append_int_noprefix(tbl, 0x7f, 4); /* Flags */\n+ build_append_int_noprefix(tbl, next_offset, 4); /* Next Level of Cache */\n+ build_append_int_noprefix(tbl, cache->size, 4); /* Size */\n+ build_append_int_noprefix(tbl, cache->sets, 4); /* Number of sets */\n+ build_append_byte(tbl, cache->associativity); /* Associativity */\n+ val = 0x3;\n+ switch (cache->type) {\n+ case INSTRUCTION_CACHE:\n+ val |= (1 << 2); /* Instruction Cache */\n+ break;\n+ case DATA_CACHE:\n+ val |= (0 << 2); /* Data Cache */\n+ break;\n+ case UNIFIED_CACHE:\n+ val |= (3 << 2); /* Unified */\n+ break;\n+ }\n+ build_append_byte(tbl, val); /* Attributes */\n+ build_append_int_noprefix(tbl, cache->linesize, 2); /* Line size */\n+ g_assert(tbl->len == start_len + node_length);\n+}\n+\n+/*\n+ * Build PPTT Cache Type structures (Type 1) from cache level `level_high`\n+ * down to `level_low` (both inclusive), appending them to the PPTT table.\n+ *\n+ * On output, `data_offset` and `instr_offset` hold the PPTT offsets of the\n+ * lowest-level data and instruction cache nodes respectively. These offsets\n+ * are referenced as private resources in the Processor Hierarchy Node (Type 0)\n+ * that owns the caches.\n+ */\n+static bool build_caches(GArray *table_data, uint32_t pptt_start,\n+ int num_caches, CPUCoreCaches *caches,\n+ uint8_t level_high, /* Inclusive */\n+ uint8_t level_low, /* Inclusive */\n+ uint32_t *data_offset,\n+ uint32_t *instr_offset)\n+{\n+ uint32_t next_level_offset_data = 0, next_level_offset_instruction = 0;\n+ uint32_t this_offset, next_offset = 0;\n+ int c, level;\n+ bool found_cache = false;\n+\n+ /* Walk caches from top to bottom */\n+ for (level = level_high; level >= level_low; level--) {\n+ for (c = 0; c < num_caches; c++) {\n+ if (caches[c].level != level) {\n+ continue;\n+ }\n+\n+ /* Assume only unified above l1 for now */\n+ this_offset = table_data->len - pptt_start;\n+ switch (caches[c].type) {\n+ case INSTRUCTION_CACHE:\n+ next_offset = next_level_offset_instruction;\n+ break;\n+ case DATA_CACHE:\n+ next_offset = next_level_offset_data;\n+ break;\n+ case UNIFIED_CACHE:\n+ /* Either is fine here */\n+ next_offset = next_level_offset_instruction;\n+ break;\n+ }\n+ build_cache_nodes(table_data, &caches[c], next_offset);\n+ switch (caches[c].type) {\n+ case INSTRUCTION_CACHE:\n+ next_level_offset_instruction = this_offset;\n+ break;\n+ case DATA_CACHE:\n+ next_level_offset_data = this_offset;\n+ break;\n+ case UNIFIED_CACHE:\n+ next_level_offset_instruction = this_offset;\n+ next_level_offset_data = this_offset;\n+ break;\n+ }\n+ *data_offset = next_level_offset_data;\n+ *instr_offset = next_level_offset_instruction;\n+\n+ found_cache = true;\n+ }\n+ }\n+\n+ return found_cache;\n+}\n+\n /*\n * ACPI spec, Revision 6.3\n * 5.2.29 Processor Properties Topology Table (PPTT)\n@@ -2160,11 +2263,31 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n {\n MachineClass *mc = MACHINE_GET_CLASS(ms);\n CPUArchIdList *cpus = ms->possible_cpus;\n- int64_t socket_id = -1, cluster_id = -1, core_id = -1;\n- uint32_t socket_offset = 0, cluster_offset = 0, core_offset = 0;\n+ uint32_t core_data_offset = 0;\n+ uint32_t core_instr_offset = 0;\n+ uint32_t cluster_instr_offset = 0;\n+ uint32_t cluster_data_offset = 0;\n+ uint32_t node_data_offset = 0;\n+ uint32_t node_instr_offset = 0;\n+ int top_node = 3;\n+ int top_cluster = 3;\n+ int top_core = 3;\n+ int bottom_node = 3;\n+ int bottom_cluster = 3;\n+ int bottom_core = 3;\n+ int64_t socket_id = -1;\n+ int64_t cluster_id = -1;\n+ int64_t core_id = -1;\n+ uint32_t socket_offset = 0;\n+ uint32_t cluster_offset = 0;\n+ uint32_t core_offset = 0;\n uint32_t pptt_start = table_data->len;\n uint32_t root_offset;\n int n;\n+ uint32_t priv_rsrc[2];\n+ uint32_t num_priv = 0;\n+ bool cache_at_topo_level;\n+\n AcpiTable table = { .sig = \"PPTT\", .rev = 2,\n .oem_id = oem_id, .oem_table_id = oem_table_id };\n \n@@ -2194,11 +2317,29 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n socket_id = cpus->cpus[n].props.socket_id;\n cluster_id = -1;\n core_id = -1;\n+ bottom_node = top_node;\n+ num_priv = 0;\n+ cache_at_topo_level =\n+ machine_find_lowest_level_cache_at_topo_level(\n+ ms, &bottom_node, CPU_TOPOLOGY_LEVEL_SOCKET);\n+ if (cache_at_topo_level) {\n+ build_caches(table_data, pptt_start, num_caches, caches,\n+ top_node, bottom_node, &node_data_offset,\n+ &node_instr_offset);\n+ priv_rsrc[0] = node_instr_offset;\n+ priv_rsrc[1] = node_data_offset;\n+ if (node_instr_offset || node_data_offset) {\n+ num_priv = node_instr_offset == node_data_offset ? 1 : 2;\n+ }\n+\n+ top_cluster = bottom_node - 1;\n+ }\n+\n socket_offset = table_data->len - pptt_start;\n build_processor_hierarchy_node(table_data,\n (1 << 0) | /* Physical package */\n (1 << 4), /* Identical Implementation */\n- root_offset, socket_id, NULL, 0);\n+ root_offset, socket_id, priv_rsrc, num_priv);\n }\n \n if (mc->smp_props.clusters_supported && mc->smp_props.has_clusters) {\n@@ -2206,21 +2347,66 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n assert(cpus->cpus[n].props.cluster_id > cluster_id);\n cluster_id = cpus->cpus[n].props.cluster_id;\n core_id = -1;\n+ bottom_cluster = top_cluster;\n+ num_priv = 0;\n+ cache_at_topo_level =\n+ machine_find_lowest_level_cache_at_topo_level(\n+ ms, &bottom_cluster, CPU_TOPOLOGY_LEVEL_CLUSTER);\n+\n+ if (cache_at_topo_level) {\n+ build_caches(table_data, pptt_start, num_caches, caches,\n+ top_cluster, bottom_cluster,\n+ &cluster_data_offset, &cluster_instr_offset);\n+ priv_rsrc[0] = cluster_instr_offset;\n+ priv_rsrc[1] = cluster_data_offset;\n+ if (cluster_instr_offset || cluster_data_offset) {\n+ num_priv =\n+ cluster_instr_offset == cluster_data_offset ? 1 : 2;\n+ }\n+ top_core = bottom_cluster - 1;\n+ } else if (top_cluster == bottom_node - 1) {\n+ /* socket cache but no cluster cache */\n+ top_core = bottom_node - 1;\n+ }\n+\n cluster_offset = table_data->len - pptt_start;\n build_processor_hierarchy_node(table_data,\n (0 << 0) | /* Not a physical package */\n (1 << 4), /* Identical Implementation */\n- socket_offset, cluster_id, NULL, 0);\n+ socket_offset, cluster_id, priv_rsrc, num_priv);\n }\n } else {\n+ if (machine_defines_cache_at_topo_level(\n+ ms, CPU_TOPOLOGY_LEVEL_CLUSTER)) {\n+ error_setg(&error_fatal, \"Not clusters found for the cache\");\n+ return;\n+ }\n+\n cluster_offset = socket_offset;\n+ top_core = bottom_node - 1; /* there is no cluster */\n+ }\n+\n+ if (cpus->cpus[n].props.core_id != core_id) {\n+ bottom_core = top_core;\n+ num_priv = 0;\n+ cache_at_topo_level =\n+ machine_find_lowest_level_cache_at_topo_level(\n+ ms, &bottom_core, CPU_TOPOLOGY_LEVEL_CORE);\n+ if (cache_at_topo_level) {\n+ build_caches(table_data, pptt_start, num_caches, caches,\n+ top_core, bottom_core, &core_data_offset,\n+ &core_instr_offset);\n+ priv_rsrc[0] = core_instr_offset;\n+ priv_rsrc[1] = core_data_offset;\n+ num_priv = core_instr_offset == core_data_offset ? 1 : 2;\n+ }\n }\n \n if (ms->smp.threads == 1) {\n build_processor_hierarchy_node(table_data,\n (1 << 1) | /* ACPI Processor ID valid */\n- (1 << 3), /* Node is a Leaf */\n- cluster_offset, n, NULL, 0);\n+ (1 << 3), /* Node is a Leaf */\n+ cluster_offset, n, priv_rsrc, num_priv);\n } else {\n if (cpus->cpus[n].props.core_id != core_id) {\n assert(cpus->cpus[n].props.core_id > core_id);\n@@ -2229,7 +2415,7 @@ void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms,\n build_processor_hierarchy_node(table_data,\n (0 << 0) | /* Not a physical package */\n (1 << 4), /* Identical Implementation */\n- cluster_offset, core_id, NULL, 0);\n+ cluster_offset, core_id, priv_rsrc, num_priv);\n }\n \n build_processor_hierarchy_node(table_data,\ndiff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex cd0700416e..41ca0bab08 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -1255,6 +1255,10 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)\n unsigned dsdt, xsdt;\n GArray *tables_blob = tables->table_data;\n MachineState *ms = MACHINE(vms);\n+ CPUCoreCaches caches[CPU_MAX_CACHES];\n+ unsigned int num_caches;\n+\n+ num_caches = virt_get_caches(vms, caches);\n \n table_offsets = g_array_new(false, true /* clear */,\n sizeof(uint32_t));\n@@ -1276,8 +1280,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)\n \n if (!vmc->no_cpu_topology) {\n acpi_add_table(table_offsets, tables_blob);\n- build_pptt(tables_blob, tables->linker, ms,\n- vms->oem_id, vms->oem_table_id, 0, NULL);\n+ build_pptt(tables_blob, tables->linker, ms, vms->oem_id,\n+ vms->oem_table_id, num_caches, caches);\n }\n \n acpi_add_table(table_offsets, tables_blob);\ndiff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h\nindex 2809dd8a91..04c821d2b9 100644\n--- a/include/hw/acpi/cpu.h\n+++ b/include/hw/acpi/cpu.h\n@@ -69,6 +69,16 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,\n \n void acpi_cpu_ospm_status(CPUHotplugState *cpu_st, ACPIOSTInfoList ***list);\n \n+struct CPUPPTTCaches {\n+ enum CacheType type;\n+ uint32_t sets;\n+ uint32_t size;\n+ uint32_t level;\n+ uint16_t linesize;\n+ uint8_t attributes; /* write policy: 0x0 write back, 0x1 write through */\n+ uint8_t associativity;\n+};\n+\n extern const VMStateDescription vmstate_cpu_hotplug;\n #define VMSTATE_CPU_HOTPLUG(cpuhp, state) \\\n VMSTATE_STRUCT(cpuhp, state, 1, \\\n", "prefixes": [ "PULL", "06/59" ] }