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GET /api/1.1/patches/2226507/?format=api
{ "id": 2226507, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2226507/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260422143112.1329478-2-raymondmaoca@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260422143112.1329478-2-raymondmaoca@gmail.com>", "date": "2026-04-22T14:30:57", "name": "[01/16] gpio: add gpio driver for Spacemit K1 SoC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d22162a1b918f54df4e7be6efd1a12faccb35eb6", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/1.1/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260422143112.1329478-2-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 501020, "url": "http://patchwork.ozlabs.org/api/1.1/series/501020/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501020", "date": "2026-04-22T14:30:56", "name": "Add PIN and SPI support for Spacemit K1", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501020/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226507/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226507/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=qZ7KD6Z0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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The GPIOs are arranged\n+\t into a number of banks (different for each SoC type) each with 32\n+\t GPIOs.\n+\n config SUNXI_GPIO\n \tbool \"Allwinner GPIO driver\"\n \tdepends on ARCH_SUNXI\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex fec258f59f5..7760aa8e11a 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -66,6 +66,7 @@ obj-$(CONFIG_MVEBU_GPIO)\t+= mvebu_gpio.o\n obj-$(CONFIG_MSM_GPIO)\t\t+= msm_gpio.o\n obj-$(CONFIG_$(PHASE_)PCF8575_GPIO)\t+= pcf8575_gpio.o\n obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO)\t+= qcom_pmic_gpio.o qcom_spmi_gpio.o\n+obj-$(CONFIG_$(PHASE_)SPACEMIT_GPIO)\t+= spacemit_gpio.o\n obj-$(CONFIG_MT7620_GPIO)\t+= mt7620_gpio.o\n obj-$(CONFIG_MT7621_GPIO)\t+= mt7621_gpio.o\n obj-$(CONFIG_MSCC_SGPIO)\t+= mscc_sgpio.o\ndiff --git a/drivers/gpio/spacemit_gpio.c b/drivers/gpio/spacemit_gpio.c\nnew file mode 100644\nindex 00000000000..02a13bd8bce\n--- /dev/null\n+++ b/drivers/gpio/spacemit_gpio.c\n@@ -0,0 +1,217 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2025-2026 RISCstar Ltd.\n+ */\n+\n+#include <asm/gpio.h>\n+#include <clk.h>\n+#include <dm/device.h>\n+#include <dm/device_compat.h>\n+#include <dm/pinctrl.h>\n+#include <dm/read.h>\n+#include <linux/bitops.h>\n+#include <linux/errno.h>\n+#include <linux/io.h>\n+#include <log.h>\n+\n+#define GPIO_BANK_SIZE\t\t32\n+#define GPIO_TO_BANK(pin)\t((pin) / GPIO_BANK_SIZE)\n+#define GPIO_TO_BIT(pin)\t((pin) % GPIO_BANK_SIZE)\n+\n+static inline int gpio_to_reg_offset(unsigned int pin)\n+{\n+\tunsigned int bank = GPIO_TO_BANK(pin);\n+\n+\tif (bank == 0)\n+\t\treturn 0;\n+\telse if (bank == 1)\n+\t\treturn 4;\n+\telse if (bank == 2)\n+\t\treturn 8;\n+\telse if (bank == 3)\n+\t\treturn 0x100;\n+\tlog_warning(\"Use default GPIO bank for an invalid GPIO[%d].\\n\", pin);\n+\treturn 0;\n+}\n+\n+#define REG_PLR(pin)\t\t(0x00 + gpio_to_reg_offset(pin))\n+#define REG_PDR(pin)\t\t(0x0c + gpio_to_reg_offset(pin))\n+#define REG_PSR(pin)\t\t(0x18 + gpio_to_reg_offset(pin))\n+#define REG_PCR(pin)\t\t(0x24 + gpio_to_reg_offset(pin))\n+#define REG_SDR(pin)\t\t(0x54 + gpio_to_reg_offset(pin))\n+#define REG_CDR(pin)\t\t(0x60 + gpio_to_reg_offset(pin))\n+\n+struct spacemit_gpio_data {\n+\tu16\tgpio_base;\n+\tu16\tgpio_count;\n+\tu8\tnum_banks;\n+};\n+\n+struct spacemit_gpio_priv {\n+\tvoid __iomem *regs;\n+};\n+\n+static int spacemit_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,\n+\t\t\t struct ofnode_phandle_args *args)\n+{\n+\tstruct spacemit_gpio_data *data;\n+\tu32 bank, offset, flags;\n+\n+\tdata = (struct spacemit_gpio_data *)dev_get_driver_data(dev);\n+\tif (args->args_count < 3) {\n+\t\tdev_err(dev, \"Invalid args count: %d, expected 3\\n\",\n+\t\t\targs->args_count);\n+\t\treturn -EINVAL;\n+\t}\n+\tbank = args->args[0];\n+\toffset = args->args[1];\n+\tflags = args->args[2];\n+\n+\tif (bank >= data->num_banks) {\n+\t\tdev_err(dev, \"Invalid gpio bank: %u (max %u)\\n\",\n+\t\t\tbank, data->num_banks - 1);\n+\t\treturn -EINVAL;\n+\t}\n+\tif (offset >= GPIO_BANK_SIZE) {\n+\t\tdev_err(dev, \"Invalid offset: %u (max 31)\\n\", offset);\n+\t\treturn -EINVAL;\n+\t}\n+\tdesc->offset = bank * GPIO_BANK_SIZE + offset;\n+\tdesc->flags = flags;\n+\treturn 0;\n+}\n+\n+static int spacemit_gpio_get_value(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct spacemit_gpio_priv *priv = dev_get_priv(dev);\n+\tvoid __iomem *addr;\n+\tu32 value, mask;\n+\n+\taddr = priv->regs + REG_PLR(offset);\n+\tvalue = readl(addr);\n+\tmask = 1 << GPIO_TO_BIT(offset);\n+\treturn !!(value & mask);\n+}\n+\n+static int spacemit_gpio_get_function(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct spacemit_gpio_priv *priv = dev_get_priv(dev);\n+\tvoid __iomem *addr;\n+\tu32 value, mask;\n+\n+\taddr = priv->regs + REG_PDR(offset);\n+\tvalue = readl(addr);\n+\tmask = 1 << GPIO_TO_BIT(offset);\n+\tif (value & mask)\n+\t\treturn GPIOF_OUTPUT;\n+\treturn GPIOF_INPUT;\n+}\n+\n+static int spacemit_gpio_get_flags(struct udevice *dev, unsigned int offset,\n+\t\t\t\t ulong *flagsp)\n+{\n+\tulong flags = 0;\n+\tu32 dir;\n+\n+\tdir = spacemit_gpio_get_function(dev, offset);\n+\tif (dir) {\n+\t\tflags |= GPIOD_IS_OUT;\n+\t\tif (spacemit_gpio_get_value(dev, offset))\n+\t\t\tflags |= GPIOD_IS_OUT_ACTIVE;\n+\t} else {\n+\t\tflags |= GPIOD_IS_IN;\n+\t}\n+\t*flagsp = flags;\n+\treturn 0;\n+}\n+\n+static int spacemit_gpio_set_flags(struct udevice *dev, unsigned int offset,\n+\t\t\t\t ulong flags)\n+{\n+\tstruct spacemit_gpio_priv *priv = dev_get_priv(dev);\n+\tvoid __iomem *addr;\n+\tint value;\n+\n+\tvalue = (flags & GPIOD_IS_OUT_ACTIVE) ? 1 : 0;\n+\tif (flags & GPIOD_IS_IN) {\n+\t\taddr = priv->regs + REG_CDR(offset);\n+\t\twritel(1 << GPIO_TO_BIT(offset), addr);\n+\t}\n+\tif (flags & GPIOD_IS_OUT) {\n+\t\tif (value) {\n+\t\t\taddr = priv->regs + REG_PSR(offset);\n+\t\t\twritel(1 << GPIO_TO_BIT(offset), addr);\n+\t\t} else {\n+\t\t\taddr = priv->regs + REG_PCR(offset);\n+\t\t\twritel(1 << GPIO_TO_BIT(offset), addr);\n+\t\t}\n+\t\taddr = priv->regs + REG_SDR(offset);\n+\t\twritel(1 << GPIO_TO_BIT(offset), addr);\n+\t}\n+\treturn 0;\n+}\n+\n+static const struct dm_gpio_ops spacemit_gpio_ops = {\n+\t.request\t= pinctrl_gpio_request,\n+\t.rfree\t\t= pinctrl_gpio_free,\n+\t.xlate\t\t= spacemit_gpio_xlate,\n+\t.get_value\t= spacemit_gpio_get_value,\n+\t.get_function\t= spacemit_gpio_get_function,\n+\t.get_flags\t= spacemit_gpio_get_flags,\n+\t.set_flags\t= spacemit_gpio_set_flags,\n+};\n+\n+static int spacemit_gpio_probe(struct udevice *dev)\n+{\n+\tstruct spacemit_gpio_priv *priv;\n+\tstruct spacemit_gpio_data *data;\n+\tstruct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);\n+\tstruct clk_bulk clks;\n+\tint ret;\n+\n+\tdata = (struct spacemit_gpio_data *)dev_get_driver_data(dev);\n+\tpriv = dev_get_priv(dev);\n+\tpriv->regs = dev_read_addr_ptr(dev);\n+\tif (!priv->regs) {\n+\t\tdev_err(dev, \"Fail to get base address\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tuc_priv->bank_name = \"GPIO\";\n+\tuc_priv->gpio_count = data->gpio_count;\n+\tuc_priv->gpio_base = data->gpio_base;\n+\n+\tret = clk_get_bulk(dev, &clks);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Fail to get bulk clks\\n\");\n+\t\treturn ret;\n+\t}\n+\tret = clk_enable_bulk(&clks);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Fail to enable bulk clks\\n\");\n+\t\tgoto out;\n+\t}\n+\treturn 0;\n+out:\n+\tclk_release_bulk(&clks);\n+\treturn ret;\n+}\n+\n+static const struct spacemit_gpio_data k1_gpio_data = {\n+\t.num_banks\t= 4,\n+\t.gpio_count\t= 128,\n+\t.gpio_base\t= 0,\n+};\n+\n+static const struct udevice_id spacemit_gpio_ids[] = {\n+\t{ .compatible = \"spacemit,k1-gpio\", .data = (uintptr_t)&k1_gpio_data, },\n+\t{ /* sentinel */ }\n+};\n+\n+U_BOOT_DRIVER(k1_gpio) = {\n+\t.name\t\t= \"spacemit_k1_gpio\",\n+\t.id\t\t= UCLASS_GPIO,\n+\t.of_match\t= spacemit_gpio_ids,\n+\t.ops\t\t= &spacemit_gpio_ops,\n+\t.priv_auto\t= sizeof(struct spacemit_gpio_priv),\n+\t.probe\t\t= spacemit_gpio_probe,\n+};\n", "prefixes": [ "01/16" ] }