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GET /api/1.1/patches/2226473/?format=api
{ "id": 2226473, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2226473/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-28-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260422125250.1303100-28-alex.bennee@linaro.org>", "date": "2026-04-22T12:52:44", "name": "[v3,27/32] target/arm: implements SEV/SEVL for all modes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bb2e90cb1d3914eaa81b83a9c6e06550dca015da", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.1/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260422125250.1303100-28-alex.bennee@linaro.org/mbox/", "series": [ { "id": 501008, "url": "http://patchwork.ozlabs.org/api/1.1/series/501008/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501008", "date": "2026-04-22T12:52:20", "name": "target/arm: fully model WFxT instructions for A-profile", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501008/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2226473/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2226473/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=B7rX85pJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32e;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Remove the restrictions that make this a M-profile only operation and\nenable the instructions for all Arm profiles.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\n---\nv2\n - fix alignment in a32.decode\n - set bool directly, defend with QEMU_BUILD_BUG_ON\n - s/instructions/profiles/\n - share get_event_reg between translate/translate-a64\n---\n target/arm/tcg/translate.h | 18 ++++++++++++++++++\n target/arm/tcg/a32.decode | 5 ++---\n target/arm/tcg/a64.decode | 5 ++---\n target/arm/tcg/t16.decode | 4 +---\n target/arm/tcg/t32.decode | 4 +---\n target/arm/tcg/op_helper.c | 4 +---\n target/arm/tcg/translate-a64.c | 17 +++++++++++++++++\n target/arm/tcg/translate.c | 13 ++++++++-----\n 8 files changed, 50 insertions(+), 20 deletions(-)", "diff": "diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h\nindex 3e3094a463e..9bf2701a56b 100644\n--- a/target/arm/tcg/translate.h\n+++ b/target/arm/tcg/translate.h\n@@ -864,6 +864,24 @@ static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)\n gen_helper_set_rmode(old, old, fpst);\n }\n \n+/*\n+ * Event Register signalling.\n+ *\n+ * A bunch of activities trigger events, we just need to latch on to\n+ * true. The event eventually gets consumed by WFE/WFET.\n+ *\n+ * user-mode treats these as NOPs.\n+ */\n+\n+static inline void gen_event_reg(void)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ TCGv_i32 set_event = tcg_constant_i32(1);\n+ QEMU_BUILD_BUG_ON(sizeof_field(CPUARMState, event_register) != 1);\n+ tcg_gen_st8_i32(set_event, tcg_env, offsetof(CPUARMState, event_register));\n+#endif\n+}\n+\n /*\n * Helpers for implementing sets of trans_* functions.\n * Defer the implementation of NAME to FUNC, with optional extra arguments.\ndiff --git a/target/arm/tcg/a32.decode b/target/arm/tcg/a32.decode\nindex f2ca4809495..547aa2b1490 100644\n--- a/target/arm/tcg/a32.decode\n+++ b/target/arm/tcg/a32.decode\n@@ -192,9 +192,8 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn\n WFE ---- 0011 0010 0000 1111 ---- 0000 0010\n WFI ---- 0011 0010 0000 1111 ---- 0000 0011\n \n- # TODO: Implement SEV, SEVL; may help SMP performance.\n- # SEV ---- 0011 0010 0000 1111 ---- 0000 0100\n- # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101\n+ SEV ---- 0011 0010 0000 1111 ---- 0000 0100\n+ SEVL ---- 0011 0010 0000 1111 ---- 0000 0101\n \n ESB ---- 0011 0010 0000 1111 ---- 0001 0000\n ]\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 01b1b3e38be..dcb3099dd5c 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -237,9 +237,8 @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB\n YIELD 1101 0101 0000 0011 0010 0000 001 11111\n WFE 1101 0101 0000 0011 0010 0000 010 11111\n WFI 1101 0101 0000 0011 0010 0000 011 11111\n- # We implement WFE to never block, so our SEV/SEVL are NOPs\n- # SEV 1101 0101 0000 0011 0010 0000 100 11111\n- # SEVL 1101 0101 0000 0011 0010 0000 101 11111\n+ SEV 1101 0101 0000 0011 0010 0000 100 11111\n+ SEVL 1101 0101 0000 0011 0010 0000 101 11111\n # Our DGL is a NOP because we don't merge memory accesses anyway.\n # DGL 1101 0101 0000 0011 0010 0000 110 11111\n XPACLRI 1101 0101 0000 0011 0010 0000 111 11111\ndiff --git a/target/arm/tcg/t16.decode b/target/arm/tcg/t16.decode\nindex 778fbf16275..9a8f89538ac 100644\n--- a/target/arm/tcg/t16.decode\n+++ b/target/arm/tcg/t16.decode\n@@ -228,10 +228,8 @@ REVSH 1011 1010 11 ... ... @rdm\n WFE 1011 1111 0010 0000\n WFI 1011 1111 0011 0000\n \n- # M-profile SEV is implemented.\n- # TODO: Implement SEV for other profiles, and SEVL for all profiles; may help SMP performance.\n SEV 1011 1111 0100 0000\n- # SEVL 1011 1111 0101 0000\n+ SEVL 1011 1111 0101 0000\n \n # The canonical nop has the second nibble as 0000, but the whole of the\n # rest of the space is a reserved hint, behaves as nop.\ndiff --git a/target/arm/tcg/t32.decode b/target/arm/tcg/t32.decode\nindex 49b8d0037ec..8ae277fe112 100644\n--- a/target/arm/tcg/t32.decode\n+++ b/target/arm/tcg/t32.decode\n@@ -369,10 +369,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm\n WFE 1111 0011 1010 1111 1000 0000 0000 0010\n WFI 1111 0011 1010 1111 1000 0000 0000 0011\n \n- # M-profile SEV is implemented.\n- # TODO: Implement SEV for other profiles, and SEVL for all profiles; may help SMP performance.\n SEV 1111 0011 1010 1111 1000 0000 0000 0100\n- # SEVL 1111 0011 1010 1111 1000 0000 0000 0101\n+ SEVL 1111 0011 1010 1111 1000 0000 0000 0101\n \n ESB 1111 0011 1010 1111 1000 0000 0001 0000\n ]\ndiff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c\nindex 46c745077d5..655e3f96e78 100644\n--- a/target/arm/tcg/op_helper.c\n+++ b/target/arm/tcg/op_helper.c\n@@ -477,9 +477,7 @@ void HELPER(sev)(CPUARMState *env)\n CPUState *cs = env_cpu(env);\n CPU_FOREACH(cs) {\n ARMCPU *target_cpu = ARM_CPU(cs);\n- if (arm_feature(&target_cpu->env, ARM_FEATURE_M)) {\n- target_cpu->env.event_register = true;\n- }\n+ target_cpu->env.event_register = true;\n if (!qemu_cpu_is_self(cs)) {\n qemu_cpu_kick(cs);\n }\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex d79c8ab431b..f30df5dbfed 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -2032,6 +2032,23 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a)\n return true;\n }\n \n+static bool trans_SEV(DisasContext *s, arg_SEV *a)\n+{\n+ /*\n+ * SEV is a NOP for user-mode emulation.\n+ */\n+#ifndef CONFIG_USER_ONLY\n+ gen_helper_sev(tcg_env);\n+#endif\n+ return true;\n+}\n+\n+static bool trans_SEVL(DisasContext *s, arg_SEV *a)\n+{\n+ gen_event_reg();\n+ return true;\n+}\n+\n static bool trans_WFE(DisasContext *s, arg_WFI *a)\n {\n /*\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex f9d1b8897d2..59925151fc3 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -3244,17 +3244,20 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)\n static bool trans_SEV(DisasContext *s, arg_SEV *a)\n {\n /*\n- * Currently SEV is a NOP for non-M-profile and in user-mode emulation.\n- * For system-mode M-profile, it sets the event register.\n+ * SEV is a NOP for user-mode emulation.\n */\n #ifndef CONFIG_USER_ONLY\n- if (arm_dc_feature(s, ARM_FEATURE_M)) {\n- gen_helper_sev(tcg_env);\n- }\n+ gen_helper_sev(tcg_env);\n #endif\n return true;\n }\n \n+static bool trans_SEVL(DisasContext *s, arg_SEV *a)\n+{\n+ gen_event_reg();\n+ return true;\n+}\n+\n static bool trans_WFE(DisasContext *s, arg_WFE *a)\n {\n /*\n", "prefixes": [ "v3", "27/32" ] }