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GET /api/1.1/patches/2225906/?format=api
{ "id": 2225906, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225906/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162856.298260-1-alexander.hansen@9elements.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260421162856.298260-1-alexander.hansen@9elements.com>", "date": "2026-04-21T16:28:56", "name": "hw/sensor: MAX31790 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "db40a25416699790fb4fc779fe185f7ca2db3a69", "submitter": { "id": 87518, "url": "http://patchwork.ozlabs.org/api/1.1/people/87518/?format=api", "name": "Alexander Hansen", "email": "alexander.hansen@9elements.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421162856.298260-1-alexander.hansen@9elements.com/mbox/", "series": [ { "id": 500884, "url": "http://patchwork.ozlabs.org/api/1.1/series/500884/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500884", "date": "2026-04-21T16:28:56", "name": "hw/sensor: MAX31790 support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500884/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225906/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225906/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=9elements.com header.i=@9elements.com header.a=rsa-sha256\n header.s=google header.b=SHIJ5I0H;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0Y7q24Brz1yJG\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 05:58:31 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wFHEL-0003M0-MB; Tue, 21 Apr 2026 15:57:57 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alexander.hansen@9elements.com>)\n id 1wFDzk-0000hy-KY\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:44 -0400", "from mail-wm1-x336.google.com ([2a00:1450:4864:20::336])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <alexander.hansen@9elements.com>)\n id 1wFDzf-0006Cc-Q7\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 12:30:40 -0400", "by mail-wm1-x336.google.com with SMTP id\n 5b1f17b1804b1-48a563e4ef7so8843135e9.0\n for <qemu-devel@nongnu.org>; Tue, 21 Apr 2026 09:30:33 -0700 (PDT)", "from alexanderarchlinux\n (ip-078-094-000-050.um19.pools.vodafone-ip.de. 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18:28:56 +0200", "Message-ID": "<20260421162856.298260-1-alexander.hansen@9elements.com>", "X-Mailer": "git-send-email 2.53.0", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::336;\n envelope-from=alexander.hansen@9elements.com; helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Tue, 21 Apr 2026 15:57:56 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Product: [1]\nDatasheet: [2]\n\nMAX31790 Support:\n- fan inputs are reading\n- tach reading propertional to pwm setting from linux driver\n- fans do not show any fault\n- 6 PWM registers influence 6 TACH registers\n\nThere is intentional stub behavior in some places and various functions\nof the device are currently unsupported.\n\nMAX31790 currently unsupported:\n- slave address restriction\n- fan dynamics\n- spin-up configuration\n- fault state / failure possibility\n- rate-of-change control\n- tach mode\n- mixed layouts where number of fans != number of tachs\n- see Figure 5.9 in [2] for example of mixed layout\n\nAnyone could expand it in the future for more accurate emulation.\n\nTested: on yosemite 4 qemu\n\n```\nroot@yosemite4:~# ls /sys/class/hwmon/hwmon2/\ndevice\t fan2_fault fan3_target fan5_fault fan6_target pwm2\t pwm5\nfan1_enable fan2_input fan4_enable fan5_input name\tpwm2_enable pwm5_enable\nfan1_fault fan2_target fan4_fault fan5_target of_node\tpwm3\t pwm6\nfan1_input fan3_enable fan4_input fan6_enable power\tpwm3_enable pwm6_enable\nfan1_target fan3_fault fan4_target fan6_fault pwm1\tpwm4\t subsystem\nfan2_enable fan3_input fan5_enable fan6_input pwm1_enable pwm4_enable uevent\nroot@yosemite4:~# cat /sys/class/hwmon/hwmon2/fan1_input\n4551\nroot@yosemite4:~# cat /sys/class/hwmon/hwmon2/fan1_enable\n1\nroot@yosemite4:~# cat /sys/class/hwmon/hwmon2/fan1_fault\n0\nroot@yosemite4:~# cat /sys/class/hwmon/hwmon2/fan1_target\n2048\nroot@yosemite4:~# cat /sys/class/hwmon/hwmon2/pwm1\n178\nroot@yosemite4:~# cat /sys/class/hwmon/hwmon2/name\nmax31790\n```\n\nTrace output:\n```\nmax31790_realize i2c_addr: 0x20\nmax31790_realize i2c_addr: 0x2f\nmax31790_realize i2c_addr: 0x20\nmax31790_realize i2c_addr: 0x2f\nmax31790_event i2c_addr: 0x20, event: 0x01\nmax31790_send i2c_addr: 0x20, data: 0x02\nmax31790_event i2c_addr: 0x20, event: 0x00\nmax31790_recv i2c_addr: 0x20, reg_addr: 0x02\nmax31790_recv_return i2c_addr: 0x20, returns: 0x08\n...\n```\n\nReferences:\n[1] https://www.analog.com/en/products/MAX31790.html\n[2] https://www.analog.com/media/en/technical-documentation/data-sheets/MAX31790.pdf\n\nCC: Paolo Bonzini <pbonzini@redhat.com>\nCC: Peter Maydell <peter.maydell@linaro.org>\nCC: \"Philippe Mathieu-Daudé\" <philmd@linaro.org>\nCC: qemu-arm@nongnu.org\nCC: qemu-devel@nongnu.org\nSigned-off-by: Alexander Hansen <alexander.hansen@9elements.com>\n---\n hw/arm/Kconfig | 1 +\n hw/sensor/Kconfig | 4 +\n hw/sensor/max31790.c | 499 +++++++++++++++++++++++++++++++++++\n hw/sensor/meson.build | 1 +\n hw/sensor/trace-events | 8 +\n include/hw/sensor/max31790.h | 7 +\n 6 files changed, 520 insertions(+)\n create mode 100644 hw/sensor/max31790.c\n create mode 100644 include/hw/sensor/max31790.h", "diff": "diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 4e50fb1111..c2483e4c63 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -552,6 +552,7 @@ config ASPEED_SOC\n select LED\n select PMBUS\n select MAX31785\n+ select MAX31790\n select FSI_APB2OPB_ASPEED\n select AT24C\n select PCI_EXPRESS\ndiff --git a/hw/sensor/Kconfig b/hw/sensor/Kconfig\nindex bc6331b4ab..ece2f2b167 100644\n--- a/hw/sensor/Kconfig\n+++ b/hw/sensor/Kconfig\n@@ -43,3 +43,7 @@ config ISL_PMBUS_VR\n config MAX31785\n bool\n depends on PMBUS\n+\n+config MAX31790\n+ bool\n+ depends on PMBUS\ndiff --git a/hw/sensor/max31790.c b/hw/sensor/max31790.c\nnew file mode 100644\nindex 0000000000..ec6bb394f4\n--- /dev/null\n+++ b/hw/sensor/max31790.c\n@@ -0,0 +1,499 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Maxim MAX31790 PMBus 6-Channel Fan Controller\n+ *\n+ * Datasheet:\n+ * https://www.analog.com/media/en/technical-documentation/data-sheets/MAX31790.pdf\n+ *\n+ * Copyright(c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/i2c/i2c.h\"\n+#include \"migration/vmstate.h\"\n+#include \"qapi/error.h\"\n+#include \"qapi/visitor.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/module.h\"\n+#include \"trace.h\"\n+#include \"hw/sensor/max31790.h\"\n+\n+#define MAX31790_NUM_FANS 6\n+#define MAX31790_NUM_TACHS 12\n+\n+#define MAX31790_REG_GLOBAL_CONFIG 0x00\n+#define MAX31790_REG_PWM_FREQ 0x01\n+\n+/* 0x02 to 0x07: N = 0 .. 5 */\n+#define MAX31790_REG_FAN_CONFIG(N) (0x02 + N)\n+\n+/* 0x08 to 0x0d: N = 0 .. 5 */\n+#define MAX31790_REG_FAN_DYNAMICS(N) (0x08 + N)\n+\n+#define MAX31790_REG_FAN_FAULT_STATUS_2 0x10\n+#define MAX31790_REG_FAN_FAULT_STATUS_1 0x11\n+#define MAX31790_REG_FAN_FAULT_MASK_2 0x12\n+#define MAX31790_REG_FAN_FAULT_MASK_1 0x13\n+#define MAX31790_REG_FAILED_FAN_OPT 0x14\n+\n+/* 0x18 to 0x2f: N = 0 .. 11 */\n+#define MAX31790_REG_TACH_COUNT_MSB(N) (0x18 + 2 * N)\n+#define MAX31790_REG_TACH_COUNT_LSB(N) (0x19 + 2 * N)\n+\n+/* 0x30 to 0x3b: N = 0 .. 5 */\n+#define MAX31790_REG_PWM_DUTY_CYCLE_MSB(N) (0x30 + 2 * N)\n+#define MAX31790_REG_PWM_DUTY_CYCLE_LSB(N) (0x31 + 2 * N)\n+\n+/* .. reserved registers ... */\n+\n+/* 0x40 to 0x4b: N = 0 .. 5 */\n+#define MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(N) (0x40 + 2 * N)\n+#define MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(N) (0x41 + 2 * N)\n+\n+/* ... 'User Byte' registers ... */\n+\n+/* 0x50 to 0x5b: N = 0 .. 5 */\n+#define MAX31790_REG_TACH_TARGET_COUNT_MSB(N) (0x50 + 2 * N)\n+#define MAX31790_REG_TACH_TARGET_COUNT_LSB(N) (0x51 + 2 * N)\n+\n+struct MAX31790State {\n+ I2CSlave i2c;\n+\n+ uint8_t fan_config[MAX31790_NUM_FANS];\n+ uint8_t fan_dynamics[MAX31790_NUM_FANS];\n+\n+ uint16_t pwm[MAX31790_NUM_FANS];\n+ uint16_t tach_target[MAX31790_NUM_FANS];\n+ uint16_t rpm[MAX31790_NUM_TACHS];\n+\n+ /* command buffer */\n+ uint8_t len;\n+ uint8_t buf[2];\n+\n+ /* output buffer */\n+ uint8_t outlen;\n+ uint8_t outbuf[2];\n+\n+ /* selected register for read/write operation */\n+ uint8_t pointer;\n+};\n+\n+struct MAX31790Class {\n+ I2CSlaveClass parent_class;\n+};\n+\n+OBJECT_DECLARE_TYPE(MAX31790State, MAX31790Class, MAX31790)\n+\n+static void max31790_read(MAX31790State *s)\n+{\n+ size_t index = 0;\n+ uint8_t out0 = 0;\n+ uint8_t out1 = 0;\n+\n+ switch (s->pointer) {\n+ case MAX31790_REG_FAN_CONFIG(0):\n+ case MAX31790_REG_FAN_CONFIG(1):\n+ case MAX31790_REG_FAN_CONFIG(2):\n+ case MAX31790_REG_FAN_CONFIG(3):\n+ case MAX31790_REG_FAN_CONFIG(4):\n+ case MAX31790_REG_FAN_CONFIG(5):\n+ out0 = s->fan_config[s->pointer - MAX31790_REG_FAN_CONFIG(0)];\n+ break;\n+ case MAX31790_REG_FAN_DYNAMICS(0):\n+ case MAX31790_REG_FAN_DYNAMICS(1):\n+ case MAX31790_REG_FAN_DYNAMICS(2):\n+ case MAX31790_REG_FAN_DYNAMICS(3):\n+ case MAX31790_REG_FAN_DYNAMICS(4):\n+ case MAX31790_REG_FAN_DYNAMICS(5):\n+ out0 = s->fan_dynamics[s->pointer - MAX31790_REG_FAN_DYNAMICS(0)];\n+ break;\n+ case MAX31790_REG_FAN_FAULT_STATUS_1:\n+ case MAX31790_REG_FAN_FAULT_STATUS_2:\n+ /* we do not have any fan fault */\n+ out0 = 0x00;\n+ out1 = 0x00;\n+ break;\n+ case MAX31790_REG_TACH_COUNT_MSB(0):\n+ case MAX31790_REG_TACH_COUNT_MSB(1):\n+ case MAX31790_REG_TACH_COUNT_MSB(2):\n+ case MAX31790_REG_TACH_COUNT_MSB(3):\n+ case MAX31790_REG_TACH_COUNT_MSB(4):\n+ case MAX31790_REG_TACH_COUNT_MSB(5):\n+ case MAX31790_REG_TACH_COUNT_MSB(6):\n+ case MAX31790_REG_TACH_COUNT_MSB(7):\n+ case MAX31790_REG_TACH_COUNT_MSB(8):\n+ case MAX31790_REG_TACH_COUNT_MSB(9):\n+ case MAX31790_REG_TACH_COUNT_MSB(10):\n+ case MAX31790_REG_TACH_COUNT_MSB(11):\n+ index = (s->pointer - MAX31790_REG_TACH_COUNT_MSB(0)) / 2;\n+ out0 = (s->rpm[index] >> 8) & 0xff;\n+ out1 = s->rpm[index] & 0xff;\n+ break;\n+\n+ case MAX31790_REG_TACH_COUNT_LSB(0):\n+ case MAX31790_REG_TACH_COUNT_LSB(1):\n+ case MAX31790_REG_TACH_COUNT_LSB(2):\n+ case MAX31790_REG_TACH_COUNT_LSB(3):\n+ case MAX31790_REG_TACH_COUNT_LSB(4):\n+ case MAX31790_REG_TACH_COUNT_LSB(5):\n+ case MAX31790_REG_TACH_COUNT_LSB(6):\n+ case MAX31790_REG_TACH_COUNT_LSB(7):\n+ case MAX31790_REG_TACH_COUNT_LSB(8):\n+ case MAX31790_REG_TACH_COUNT_LSB(9):\n+ case MAX31790_REG_TACH_COUNT_LSB(10):\n+ case MAX31790_REG_TACH_COUNT_LSB(11):\n+ index = (s->pointer - MAX31790_REG_TACH_COUNT_LSB(0)) / 2;\n+ out0 = s->rpm[index] & 0xff;\n+ break;\n+\n+ case MAX31790_REG_PWM_DUTY_CYCLE_MSB(0):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_MSB(1):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_MSB(2):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_MSB(3):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_MSB(4):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_MSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_DUTY_CYCLE_MSB(0)) / 2;\n+ out0 = (s->pwm[index] >> 8) & 0xff;\n+ out1 = s->pwm[index] & 0xff;\n+ break;\n+ case MAX31790_REG_PWM_DUTY_CYCLE_LSB(0):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_LSB(1):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_LSB(2):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_LSB(3):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_LSB(4):\n+ case MAX31790_REG_PWM_DUTY_CYCLE_LSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_DUTY_CYCLE_LSB(0)) / 2;\n+ out0 = s->pwm[index] & 0xff;\n+ break;\n+\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(0):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(1):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(2):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(3):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(4):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(0)) / 2;\n+ out0 = (s->pwm[index] >> 8) & 0xff;\n+ out1 = s->pwm[index] & 0xff;\n+ break;\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(0):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(1):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(2):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(3):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(4):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(0)) / 2;\n+ out0 = s->pwm[index] & 0xff;\n+ break;\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(0):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(1):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(2):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(3):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(4):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(5):\n+ index = (s->pointer - MAX31790_REG_TACH_TARGET_COUNT_MSB(0)) / 2;\n+ out0 = (s->tach_target[index] >> 8) & 0xff;\n+ out1 = s->tach_target[index] & 0xff;\n+ break;\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(0):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(1):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(2):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(3):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(4):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(5):\n+ index = (s->pointer - MAX31790_REG_TACH_TARGET_COUNT_LSB(0)) / 2;\n+ out0 = s->tach_target[index] & 0xff;\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP, \"%s: read of register %d\", __func__,\n+ s->pointer);\n+ break;\n+ }\n+\n+ s->outbuf[0] = out0;\n+ s->outbuf[1] = out1;\n+}\n+\n+static void max31790_set_rpm(MAX31790State *s, size_t index, uint16_t rpm)\n+{\n+ /* datasheet: lowest 5 bits are 0 */\n+ s->rpm[index] = rpm & ~0b11111;\n+}\n+\n+static void max31790_pwm_write(MAX31790State *s, size_t index, uint16_t value)\n+{\n+ trace_max31790_pwm_write(s->i2c.address, index, value);\n+\n+ s->pwm[index] = value;\n+\n+ /* change rpm based on pwm input */\n+ const uint16_t pwm_no_reserve = s->pwm[index] >> 7;\n+\n+ /*\n+ * This formula has magic values which model the relationship\n+ * of PWM input to a fan. Not derived from datasheet.\n+ */\n+ max31790_set_rpm(s, index, 0x1000 + (pwm_no_reserve << 3));\n+}\n+\n+static void max31790_write_2_byte(MAX31790State *s)\n+{\n+ size_t index = 0;\n+ const uint8_t value0 = s->buf[0];\n+ const uint8_t value1 = s->buf[1];\n+ switch (s->pointer) {\n+ case MAX31790_REG_FAN_CONFIG(0):\n+ case MAX31790_REG_FAN_CONFIG(1):\n+ case MAX31790_REG_FAN_CONFIG(2):\n+ case MAX31790_REG_FAN_CONFIG(3):\n+ case MAX31790_REG_FAN_CONFIG(4):\n+ case MAX31790_REG_FAN_CONFIG(5):\n+ break; /* handled by one byte write */\n+ case MAX31790_REG_FAN_DYNAMICS(0):\n+ case MAX31790_REG_FAN_DYNAMICS(1):\n+ case MAX31790_REG_FAN_DYNAMICS(2):\n+ case MAX31790_REG_FAN_DYNAMICS(3):\n+ case MAX31790_REG_FAN_DYNAMICS(4):\n+ case MAX31790_REG_FAN_DYNAMICS(5):\n+ break; /* handled by one byte write */\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(0):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(1):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(2):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(3):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(4):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(0)) / 2;\n+ max31790_pwm_write(s, index, value0 << 8 | value1);\n+ break;\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(0):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(1):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(2):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(3):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(4):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(5):\n+ index = (s->pointer - MAX31790_REG_TACH_TARGET_COUNT_MSB(0)) / 2;\n+ s->tach_target[index] = (value0 << 8) | value1;\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP, \"%s: write to register %d\", __func__,\n+ s->pointer);\n+ break;\n+ }\n+}\n+\n+static void max31790_write_1_byte(MAX31790State *s)\n+{\n+\n+ size_t index = 0;\n+ uint16_t pwm = 0;\n+ const uint8_t value = s->buf[0];\n+ switch (s->pointer) {\n+ case MAX31790_REG_FAN_CONFIG(0):\n+ case MAX31790_REG_FAN_CONFIG(1):\n+ case MAX31790_REG_FAN_CONFIG(2):\n+ case MAX31790_REG_FAN_CONFIG(3):\n+ case MAX31790_REG_FAN_CONFIG(4):\n+ case MAX31790_REG_FAN_CONFIG(5):\n+ s->fan_config[s->pointer - MAX31790_REG_FAN_CONFIG(0)] = value;\n+ break;\n+ case MAX31790_REG_FAN_DYNAMICS(0):\n+ case MAX31790_REG_FAN_DYNAMICS(1):\n+ case MAX31790_REG_FAN_DYNAMICS(2):\n+ case MAX31790_REG_FAN_DYNAMICS(3):\n+ case MAX31790_REG_FAN_DYNAMICS(4):\n+ case MAX31790_REG_FAN_DYNAMICS(5):\n+ s->fan_dynamics[s->pointer - MAX31790_REG_FAN_DYNAMICS(0)] = value;\n+ break;\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(0):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(1):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(2):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(3):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(4):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_TARGET_DUTY_CYCLE_MSB(0)) / 2;\n+ pwm = (value << 8) | (s->pwm[index] & 0x00ff);\n+ max31790_pwm_write(s, index, pwm);\n+ break;\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(0):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(1):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(2):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(3):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(4):\n+ case MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(5):\n+ index = (s->pointer - MAX31790_REG_PWM_TARGET_DUTY_CYCLE_LSB(0)) / 2;\n+ pwm = (s->pwm[index] & 0xff00) | (value & 0x00ff);\n+ max31790_pwm_write(s, index, pwm);\n+ break;\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(0):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(1):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(2):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(3):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(4):\n+ case MAX31790_REG_TACH_TARGET_COUNT_MSB(5):\n+ index = (s->pointer - MAX31790_REG_TACH_TARGET_COUNT_MSB(0)) / 2;\n+ s->tach_target[index] =\n+ (s->tach_target[index] & 0x00ff) | (value << 8);\n+ break;\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(0):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(1):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(2):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(3):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(4):\n+ case MAX31790_REG_TACH_TARGET_COUNT_LSB(5):\n+ index = (s->pointer - MAX31790_REG_TACH_TARGET_COUNT_LSB(0)) / 2;\n+ s->tach_target[index] = (s->tach_target[index] & 0xff00) | value;\n+ break;\n+ default:\n+ qemu_log_mask(LOG_UNIMP, \"%s: write to register %d\", __func__,\n+ s->pointer);\n+ break;\n+ }\n+}\n+\n+static int max31790_send(I2CSlave *i2c, uint8_t data)\n+{\n+ MAX31790State *s = MAX31790(i2c);\n+\n+ trace_max31790_send(s->i2c.address, data);\n+\n+ if (s->len == 0) {\n+ /* first byte is the register pointer for a read / write operation */\n+ s->pointer = data;\n+ s->len++;\n+ return 0;\n+ }\n+\n+ if (s->len > 2) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"%s: write too many bytes\", __func__);\n+ return 1; /* NAK */\n+ }\n+\n+ /* second / third byte is the data to write */\n+ s->buf[s->len - 1] = data;\n+ s->len++;\n+\n+ if (s->len == 2) {\n+ max31790_write_1_byte(s);\n+ } else if (s->len == 3) {\n+ max31790_write_2_byte(s);\n+ }\n+\n+ return 0;\n+}\n+\n+static uint8_t max31790_recv(I2CSlave *i2c)\n+{\n+ MAX31790State *s = MAX31790(i2c);\n+ trace_max31790_recv(s->i2c.address, s->pointer);\n+\n+ max31790_read(s);\n+ s->len = 0;\n+\n+ if (s->outlen >= 2) {\n+ /* error */\n+ s->outlen = 0;\n+ }\n+\n+ const uint8_t data = s->outbuf[s->outlen++];\n+\n+ trace_max31790_recv_return(s->i2c.address, data);\n+ return data;\n+}\n+\n+static int max31790_event(I2CSlave *i2c, enum i2c_event event)\n+{\n+ MAX31790State *s = MAX31790(i2c);\n+\n+ trace_max31790_event(s->i2c.address, event);\n+\n+ switch (event) {\n+ case I2C_START_RECV:\n+ s->outlen = 0;\n+ break;\n+ case I2C_START_SEND:\n+ s->len = 0;\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return 0;\n+}\n+\n+static const VMStateDescription vmstate_max31790 = {\n+ .name = TYPE_MAX31790,\n+ .version_id = 0,\n+ .minimum_version_id = 0,\n+ .fields = (const VMStateField[]){\n+ VMSTATE_UINT8(len, MAX31790State),\n+ VMSTATE_UINT8_ARRAY(fan_config, MAX31790State, MAX31790_NUM_FANS),\n+ VMSTATE_UINT8_ARRAY(fan_dynamics, MAX31790State, MAX31790_NUM_FANS),\n+ VMSTATE_UINT16_ARRAY(pwm, MAX31790State, MAX31790_NUM_FANS),\n+ VMSTATE_UINT16_ARRAY(tach_target, MAX31790State, MAX31790_NUM_FANS),\n+ VMSTATE_UINT16_ARRAY(rpm, MAX31790State, MAX31790_NUM_TACHS),\n+ VMSTATE_UINT8_ARRAY(buf, MAX31790State, 2),\n+ VMSTATE_UINT8(outlen, MAX31790State),\n+ VMSTATE_UINT8_ARRAY(outbuf, MAX31790State, 2),\n+ VMSTATE_UINT8(pointer, MAX31790State),\n+ VMSTATE_I2C_SLAVE(i2c, MAX31790State),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static void max31790_init(Object *obj)\n+{\n+ /* Nothing to do */\n+}\n+\n+static void max31790_realize(DeviceState *dev, Error **errp)\n+{\n+ MAX31790State *s = MAX31790(dev);\n+\n+ trace_max31790_realize(s->i2c.address);\n+\n+ for (int i = 0; i < MAX31790_NUM_FANS; i++) {\n+ /* POR-State 0b 0XX0 0000 */\n+ s->fan_config[i] = 0b00000000;\n+\n+ /* same as POR-State */\n+ s->tach_target[i] = 0b0011110000000000;\n+\n+ /* same as POR-State */\n+ s->fan_dynamics[i] = 0b01001100;\n+\n+ s->pwm[i] = 0;\n+ }\n+\n+ for (int i = 0; i < MAX31790_NUM_TACHS; i++) {\n+ max31790_set_rpm(s, i, 0x4444);\n+ }\n+}\n+\n+static void max31790_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);\n+\n+ dc->realize = max31790_realize;\n+ dc->desc = \"Maxim MAX31790 6-Channel Fan Controller\";\n+ dc->vmsd = &vmstate_max31790;\n+ k->event = max31790_event;\n+ k->recv = max31790_recv;\n+ k->send = max31790_send;\n+}\n+\n+static const TypeInfo max31790_info = {\n+ .name = TYPE_MAX31790,\n+ .parent = TYPE_I2C_SLAVE,\n+ .instance_size = sizeof(MAX31790State),\n+ .class_size = sizeof(MAX31790Class),\n+ .instance_init = max31790_init,\n+ .class_init = max31790_class_init,\n+};\n+\n+static void max31790_register_types(void)\n+{\n+ type_register_static(&max31790_info);\n+}\n+\n+type_init(max31790_register_types)\ndiff --git a/hw/sensor/meson.build b/hw/sensor/meson.build\nindex 420fdc3359..4987c3b253 100644\n--- a/hw/sensor/meson.build\n+++ b/hw/sensor/meson.build\n@@ -8,3 +8,4 @@ system_ss.add(when: 'CONFIG_MAX34451', if_true: files('max34451.c'))\n system_ss.add(when: 'CONFIG_LSM303DLHC_MAG', if_true: files('lsm303dlhc_mag.c'))\n system_ss.add(when: 'CONFIG_ISL_PMBUS_VR', if_true: files('isl_pmbus_vr.c'))\n system_ss.add(when: 'CONFIG_MAX31785', if_true: files('max31785.c'))\n+system_ss.add(when: 'CONFIG_MAX31790', if_true: files('max31790.c'))\ndiff --git a/hw/sensor/trace-events b/hw/sensor/trace-events\nindex a3fe54fa6d..c15c0a7e93 100644\n--- a/hw/sensor/trace-events\n+++ b/hw/sensor/trace-events\n@@ -4,3 +4,11 @@\n tmp105_read(uint8_t dev, uint8_t addr) \"device: 0x%02x, addr: 0x%02x\"\n tmp105_write(uint8_t dev, uint8_t addr) \"device: 0x%02x, addr 0x%02x\"\n tmp105_write_shutdown(uint8_t dev) \"device: 0x%02x\"\n+\n+# max31790.c\n+max31790_send(uint8_t i2c_addr, uint8_t send) \"i2c_addr: 0x%02x, data: 0x%02x\"\n+max31790_recv(uint8_t i2c_addr, uint8_t reg_addr) \"i2c_addr: 0x%02x, reg_addr: 0x%02x\"\n+max31790_recv_return(uint8_t i2c_addr, uint8_t data) \"i2c_addr: 0x%02x, returns: 0x%02x\"\n+max31790_event(uint8_t i2c_addr, uint8_t event) \"i2c_addr: 0x%02x, event: 0x%02x\"\n+max31790_realize(uint8_t i2c_addr) \"i2c_addr: 0x%02x\"\n+max31790_pwm_write(uint8_t i2c_addr, size_t index, uint16_t value) \"i2c_addr: 0x%02x, index: %zu, value: 0x%04x\"\ndiff --git a/include/hw/sensor/max31790.h b/include/hw/sensor/max31790.h\nnew file mode 100644\nindex 0000000000..7ead420926\n--- /dev/null\n+++ b/include/hw/sensor/max31790.h\n@@ -0,0 +1,7 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+#ifndef QEMU_MAX31790_H\n+#define QEMU_MAX31790_H\n+\n+#define TYPE_MAX31790 \"max31790\"\n+\n+#endif\n", "prefixes": [] }