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GET /api/1.1/patches/2225794/?format=api
{ "id": 2225794, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225794/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260421151604.1141082-3-ghidoliemanuele@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260421151604.1141082-3-ghidoliemanuele@gmail.com>", "date": "2026-04-21T15:15:56", "name": "[v1,2/2] board: toradex: aquila-am69: Fix memory size setup logic", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "72d31c1519243663993942097ad6c91f1b51c7d6", "submitter": { "id": 85913, "url": "http://patchwork.ozlabs.org/api/1.1/people/85913/?format=api", "name": "Emanuele Ghidoli", "email": "ghidoliemanuele@gmail.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.1/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260421151604.1141082-3-ghidoliemanuele@gmail.com/mbox/", "series": [ { "id": 500838, "url": "http://patchwork.ozlabs.org/api/1.1/series/500838/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500838", "date": "2026-04-21T15:15:54", "name": "board: toradex: aquila-am69: Fix 16GB dual-rank DDR cfg and memory size detection", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500838/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225794/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225794/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ZRP1E0r0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.b=\"ZRP1E0r0\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=ghidoliemanuele@gmail.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0QtP67PKz1yGt\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 22 Apr 2026 01:16:29 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 45898840A9;\n\tTue, 21 Apr 2026 17:16:18 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 20B4284359; Tue, 21 Apr 2026 17:16:16 +0200 (CEST)", "from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com\n [IPv6:2a00:1450:4864:20::32f])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B74F9840A9\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 17:16:13 +0200 (CEST)", "by mail-wm1-x32f.google.com with SMTP id\n 5b1f17b1804b1-488ff90d6c7so34104945e9.2\n for <u-boot@lists.denx.de>; Tue, 21 Apr 2026 08:16:13 -0700 (PDT)", "from emanueleg-nb.corp.toradex.com\n (248.201.173.83.static.wline.lns.sme.cust.swisscom.ch. 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5b1f17b1804b1-488fb7856b9mr198668755e9.20.1776784572981;\n Tue, 21 Apr 2026 08:16:12 -0700 (PDT)", "From": "Emanuele Ghidoli <ghidoliemanuele@gmail.com>", "To": "Francesco Dolcini <francesco.dolcini@toradex.com>,\n Tom Rini <trini@konsulko.com>", "Cc": "Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n\tu-boot@lists.denx.de", "Subject": "[PATCH v1 2/2] board: toradex: aquila-am69: Fix memory size setup\n logic", "Date": "Tue, 21 Apr 2026 17:15:56 +0200", "Message-ID": "<20260421151604.1141082-3-ghidoliemanuele@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260421151604.1141082-1-ghidoliemanuele@gmail.com>", "References": "<20260421151604.1141082-1-ghidoliemanuele@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>\n\nThe hardware configuration pins are used both to select the DDR\nconfiguration and to determine the installed memory size.\n\nOn Aquila AM69, the DDR timing patch is applied in the R5 SPL, while the\nmemory size fixup for the next-stage U-Boot DT is done later in the A72\nSPL path.\nThe previous immplementation was not taking in account that the hw_cfg\nvalue is lost both during SPL execution (board_init_f and board_init_r)\nand between SPL and U-Boot proper.\n\nFix this by reading the hardware configuration pins when the memory size\nis actually needed:\n- in the R5 SPL, to select the correct DDR configuration\n- in the A72 SPL, to fix up the U-Boot DT memory size and bank layout\n\nFixes: 3f0528882c0d (\"board: toradex: add aquila am69 support\")\nSigned-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>\n---\n board/toradex/aquila-am69/aquila-am69.c | 90 +++++++++++++++----------\n 1 file changed, 54 insertions(+), 36 deletions(-)", "diff": "diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c\nindex 0c7123a059e4..45fba1bbfe80 100644\n--- a/board/toradex/aquila-am69/aquila-am69.c\n+++ b/board/toradex/aquila-am69/aquila-am69.c\n@@ -15,6 +15,7 @@\n #include <i2c.h>\n #include <linux/sizes.h>\n #include <spl.h>\n+#include <asm/arch/k3-ddr.h>\n \n #include \"../common/tdx-common.h\"\n #include \"aquila_ddrs.h\"\n@@ -30,46 +31,24 @@\n #define HW_CFG_MEM_CFG_MASK\t\t0x03\n \n DECLARE_GLOBAL_DATA_PTR;\n-static u8 hw_cfg;\n \n-static u8 aquila_am69_memory_cfg(void)\n-{\n-\treturn hw_cfg & HW_CFG_MEM_CFG_MASK;\n-}\n-\n-static u64 aquila_am69_memory_size(void)\n-{\n-\tswitch (aquila_am69_memory_cfg()) {\n-\tcase HW_CFG_MEM_SZ_32GB:\n-\t\treturn SZ_32G;\n-\tcase HW_CFG_MEM_SZ_16GB_RANK_2:\n-\tcase HW_CFG_MEM_SZ_16GB:\n-\t\treturn SZ_16G;\n-\tcase HW_CFG_MEM_SZ_8GB:\n-\t\treturn SZ_8G;\n-\tdefault:\n-\t\tputs(\"Invalid memory size configuration\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-}\n-\n-static void read_hw_cfg(void)\n+static u8 get_hw_cfg(void)\n {\n \tstruct gpio_desc gpio_hw_cfg;\n \tchar gpio_name[20];\n+\tu8 hw_cfg = 0;\n \tint i;\n \n-\tprintf(\"HW CFG: \");\n \tfor (i = 0; i < 5; i++) {\n \t\tsprintf(gpio_name, \"gpio@42110000_%d\", 82 + i);\n \t\tif (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) {\n \t\t\tprintf(\"Lookup named gpio error\\n\");\n-\t\t\treturn;\n+\t\t\treturn 0;\n \t\t}\n \n \t\tif (dm_gpio_request(&gpio_hw_cfg, \"hw_cfg\")) {\n \t\t\tprintf(\"gpio request error\\n\");\n-\t\t\treturn;\n+\t\t\treturn 0;\n \t\t}\n \n \t\tif (dm_gpio_get_value(&gpio_hw_cfg) == 1)\n@@ -77,15 +56,34 @@ static void read_hw_cfg(void)\n \n \t\tdm_gpio_free(NULL, &gpio_hw_cfg);\n \t}\n-\tprintf(\"0x%02x\\n\", hw_cfg);\n+\treturn hw_cfg;\n }\n \n-static void update_ddr_timings(void)\n+static u64 aquila_am69_memory_size(void)\n+{\n+\tu8 hw_cfg = get_hw_cfg();\n+\n+\tswitch (hw_cfg & HW_CFG_MEM_CFG_MASK) {\n+\tcase HW_CFG_MEM_SZ_32GB:\n+\t\treturn SZ_32G;\n+\tcase HW_CFG_MEM_SZ_16GB_RANK_2:\n+\tcase HW_CFG_MEM_SZ_16GB:\n+\t\treturn SZ_16G;\n+\tcase HW_CFG_MEM_SZ_8GB:\n+\t\treturn SZ_8G;\n+\tdefault:\n+\t\tputs(\"Invalid memory size configuration\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+#if defined(CONFIG_TARGET_AQUILA_AM69_R5)\n+static void update_ddr_timings(u8 hw_cfg)\n {\n \tint ret = 0;\n \tvoid *fdt = (void *)gd->fdt_blob;\n \n-\tswitch (aquila_am69_memory_cfg()) {\n+\tswitch (hw_cfg & HW_CFG_MEM_CFG_MASK) {\n \tcase HW_CFG_MEM_SZ_8GB:\n \t\tret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB,\n \t\t\t\t\t\t MULTI_DDR_CFG_INTRLV_SIZE_8GB);\n@@ -103,6 +101,7 @@ static void update_ddr_timings(void)\n \tif (ret)\n \t\tprintf(\"Applying DDR patch error: %d\\n\", ret);\n }\n+#endif\n \n static int aquila_am69_fdt_fixup_memory_size(u64 total_sz)\n {\n@@ -121,21 +120,33 @@ static int aquila_am69_fdt_fixup_memory_size(u64 total_sz)\n \treturn fdt_fixup_memory_banks(blob, s, e, CONFIG_NR_DRAM_BANKS);\n }\n \n+#if defined(CONFIG_TARGET_AQUILA_AM69_R5)\n void do_board_detect(void)\n {\n+\tu8 hw_cfg;\n+\n \t/* MCU_ADC1 pins used as General Purpose Inputs */\n \twritel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16),\n \t CTRL_MMR_CFG0_MCU_ADC1_CTRL);\n \n-\tread_hw_cfg();\n+\thw_cfg = get_hw_cfg();\n+\tprintf(\"HW CFG: 0x%02x\\n\", hw_cfg);\n \n \tif (IS_ENABLED(CONFIG_K3_DDRSS))\n-\t\tupdate_ddr_timings();\n+\t\tupdate_ddr_timings(hw_cfg);\n }\n+#endif\n+\n+#if defined(CONFIG_XPL_BUILD)\n+void spl_perform_board_fixups(struct spl_image_info *spl_image)\n+{\n+\tfixup_memory_node(spl_image);\n+}\n+#endif\n \n int dram_init(void)\n {\n-\ts32 ret;\n+\tint ret;\n \n \tret = fdtdec_setup_mem_size_base_lowest();\n \tif (ret)\n@@ -146,11 +157,18 @@ int dram_init(void)\n \n int dram_init_banksize(void)\n {\n-\ts32 ret;\n+\tint ret;\n \n-\tret = aquila_am69_fdt_fixup_memory_size(aquila_am69_memory_size());\n-\tif (ret)\n-\t\tprintf(\"Error setting memory size. %d\\n\", ret);\n+\tif (IS_ENABLED(CONFIG_SPL_BUILD) &&\n+\t IS_ENABLED(CONFIG_TARGET_AQUILA_AM69_A72)) {\n+\t\tu64 mem_sz = aquila_am69_memory_size();\n+\n+\t\tret = aquila_am69_fdt_fixup_memory_size(mem_sz);\n+\t\tif (ret)\n+\t\t\tprintf(\"Error setting memory size. %d\\n\", ret);\n+\t} else {\n+\t\tfdtdec_setup_mem_size_base();\n+\t}\n \n \tret = fdtdec_setup_memory_banksize();\n \tif (ret)\n", "prefixes": [ "v1", "2/2" ] }