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Update a patch.
GET /api/1.1/patches/2225692/?format=api
{ "id": 2225692, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225692/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-15-0e2b490542b1@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260421-imx8mq-dm-pmic-v1-15-0e2b490542b1@nxp.com>", "date": "2026-04-21T13:41:27", "name": "[15/15] imx8mq: phanbell: enable SPL DM", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "ed5c913f2733e611fa271ce30ae1766d7ff4ee51", "submitter": { "id": 80723, "url": "http://patchwork.ozlabs.org/api/1.1/people/80723/?format=api", "name": "Peng Fan", "email": "peng.fan@oss.nxp.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/1.1/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260421-imx8mq-dm-pmic-v1-15-0e2b490542b1@nxp.com/mbox/", "series": [ { "id": 500790, "url": "http://patchwork.ozlabs.org/api/1.1/series/500790/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=500790", "date": "2026-04-21T13:41:12", "name": "i.MX8MQ: Convert to DM_PMIC for a few boards", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500790/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225692/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225692/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=MWuEL+Tk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=oss.nxp.com; dmarc=pass action=none header.from=oss.nxp.com;\n dkim=pass header.d=oss.nxp.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=NXP1.onmicrosoft.com;\n s=selector1-NXP1-onmicrosoft-com;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=wxsUyudA7CNqqIy/D0hE2Vc+f5B3aGUkS25h52+OkWo=;\n b=MWuEL+TkFC8zfrwpajFIWvRwafLr8dB5fKVd5A4nCab12wMIv6RYuYvBExjCGEoaCycdvgbPHeA7j4v+PwrExkLpc/boJeEu57+bWJgPph5VRdnmunU+RG++DaHoWBt/yE3qaoxd2BCX3CwbHk+J6PB1qQ8ymFpHt0FMOIOu/EBlq7RZk/kW/A8P+hVOY7uhEvKbLChbMyJl3M5SjeVPHB+nbrXG+GOTAUTFZaaQJGcmmeVQZD4oAo85kAM5qkWx5NnE+/IsucAS8r9tSmcN8yxj7lwDfsgcna9WDg0wRsqqS3au/wkapqaPCPHf1MN9sEBEIi3KCQWztaMtb7HrAw==", "From": "\"Peng Fan (OSS)\" <peng.fan@oss.nxp.com>", "Date": "Tue, 21 Apr 2026 21:41:27 +0800", "Subject": "[PATCH 15/15] imx8mq: phanbell: enable SPL DM", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260421-imx8mq-dm-pmic-v1-15-0e2b490542b1@nxp.com>", "References": "<20260421-imx8mq-dm-pmic-v1-0-0e2b490542b1@nxp.com>", "In-Reply-To": "<20260421-imx8mq-dm-pmic-v1-0-0e2b490542b1@nxp.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n kernel@puri.sm", "Cc": "Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Tom Rini <trini@konsulko.com>, Yannic Moog <y.moog@phytec.de>,\n Ye Li <ye.li@nxp.com>, Ilias Apalodimas <ilias.apalodimas@linaro.org>,\n Alice Guo <alice.guo@nxp.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Marco Franchi <marcofrk@gmail.com>, Alifer Moraes <alifer.wsdm@gmail.com>,\n \"Lukas F. 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With DM handling MMC and power rails,\nremove legacy board-specific USDHC, GPIO, and pad setup code from SPL.\n\nUpdate the SPL initialization sequence to use spl_early_init(), clears\nBSS earlier, and explicitly enables USDHC clocks before handing off to\nboard_init_r().\n\nSigned-off-by: Peng Fan <peng.fan@nxp.com>\n---\n arch/arm/dts/imx8mq-phanbell-u-boot.dtsi | 41 +++++++++++\n board/google/imx8mq_phanbell/spl.c | 123 ++-----------------------------\n configs/imx8mq_phanbell_defconfig | 13 ++--\n 3 files changed, 56 insertions(+), 121 deletions(-)", "diff": "diff --git a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi\nindex 05f809c035d..11b81f0bbb9 100644\n--- a/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi\n+++ b/arch/arm/dts/imx8mq-phanbell-u-boot.dtsi\n@@ -2,7 +2,12 @@\n \n #include \"imx8mq-u-boot.dtsi\"\n \n+&gpio2 {\n+\tbootph-pre-ram;\n+};\n+\n ®_usdhc2_vmmc {\n+\tbootph-pre-ram;\n \tu-boot,off-on-delay-us = <20000>;\n };\n \n@@ -13,3 +18,39 @@\n &pinctrl_uart1 {\n \tbootph-pre-ram;\n };\n+\n+&usdhc1 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1_100mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc1_200mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&usdhc2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2 {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_100mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_200mhz {\n+\tbootph-pre-ram;\n+};\n+\n+&pinctrl_usdhc2_gpio {\n+\tbootph-pre-ram;\n+};\ndiff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c\nindex 642167bca59..f3aae9256c1 100644\n--- a/board/google/imx8mq_phanbell/spl.c\n+++ b/board/google/imx8mq_phanbell/spl.c\n@@ -6,22 +6,13 @@\n \n #include <config.h>\n #include <hang.h>\n-#include <asm/io.h>\n #include <errno.h>\n #include <init.h>\n #include <log.h>\n-#include <asm/io.h>\n #include <asm/arch/ddr.h>\n-#include <asm/arch/imx8mq_pins.h>\n #include <asm/arch/sys_proto.h>\n #include <asm/arch/clock.h>\n-#include <asm/mach-imx/iomux-v3.h>\n-#include <asm/mach-imx/gpio.h>\n-#include <asm/mach-imx/mxc_i2c.h>\n #include <asm/sections.h>\n-#include <linux/delay.h>\n-#include <fsl_esdhc_imx.h>\n-#include <mmc.h>\n #include <spl.h>\n \n static void spl_dram_init(void)\n@@ -30,107 +21,6 @@ static void spl_dram_init(void)\n \tddr_init(&dram_timing);\n }\n \n-#define USDHC2_CD_GPIO\tIMX_GPIO_NR(2, 12)\n-#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)\n-#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)\n-\n-int board_mmc_getcd(struct mmc *mmc)\n-{\n-\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n-\tint ret = 0;\n-\n-\tswitch (cfg->esdhc_base) {\n-\tcase USDHC1_BASE_ADDR:\n-\t\tret = 1;\n-\t\tbreak;\n-\tcase USDHC2_BASE_ADDR:\n-\t\tret = !gpio_get_value(USDHC2_CD_GPIO);\n-\t\treturn ret;\n-\t}\n-\n-\treturn 1;\n-}\n-\n-#define USDHC_PAD_CTRL\t(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \\\n-\t\t\t PAD_CTL_FSEL2)\n-#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)\n-\n-static iomux_v3_cfg_t const usdhc1_pads[] = {\n-\tIMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),\n-\tIMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),\n-};\n-\n-static iomux_v3_cfg_t const usdhc2_pads[] = {\n-\tIMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */\n-\tIMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */\n-\tIMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),\n-\tIMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),\n-};\n-\n-static struct fsl_esdhc_cfg usdhc_cfg[2] = {\n-\t{USDHC1_BASE_ADDR},\n-\t{USDHC2_BASE_ADDR},\n-};\n-\n-int board_mmc_init(struct bd_info *bis)\n-{\n-\tint i, ret;\n-\t/*\n-\t * According to the board_mmc_init() the following map is done:\n-\t * (U-Boot device node) (Physical Port)\n-\t * mmc0 USDHC1\n-\t * mmc1 USDHC2\n-\t */\n-\tfor (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {\n-\t\tswitch (i) {\n-\t\tcase 0:\n-\t\t\tinit_clk_usdhc(0);\n-\t\t\tusdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);\n-\t\t\tusdhc_cfg[0].max_bus_width = 8;\n-\t\t\timx_iomux_v3_setup_multiple_pads(usdhc1_pads,\n-\t\t\t\t\t\t\t ARRAY_SIZE(usdhc1_pads));\n-\t\t\tgpio_request(USDHC1_PWR_GPIO, \"usdhc1_reset\");\n-\t\t\tgpio_direction_output(USDHC1_PWR_GPIO, 0);\n-\t\t\tudelay(500);\n-\t\t\tgpio_direction_output(USDHC1_PWR_GPIO, 1);\n-\t\t\tbreak;\n-\t\tcase 1:\n-\t\t\tinit_clk_usdhc(1);\n-\t\t\tusdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);\n-\t\t\tusdhc_cfg[1].max_bus_width = 4;\n-\t\t\timx_iomux_v3_setup_multiple_pads(usdhc2_pads,\n-\t\t\t\t\t\t\t ARRAY_SIZE(usdhc2_pads));\n-\t\t\tgpio_request(USDHC2_PWR_GPIO, \"usdhc2_reset\");\n-\t\t\tgpio_direction_output(USDHC2_PWR_GPIO, 0);\n-\t\t\tudelay(500);\n-\t\t\tgpio_direction_output(USDHC2_PWR_GPIO, 1);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Warning: you configured more USDHC controllers(%d) than supported by the board\\n\", i + 1);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n void spl_board_init(void)\n {\n \tputs(\"Normal Boot\\n\");\n@@ -150,6 +40,9 @@ void board_init_f(ulong dummy)\n {\n \tint ret;\n \n+\t/* Clear the BSS. */\n+\tmemset(__bss_start, 0, __bss_end - __bss_start);\n+\n \tarch_cpu_init();\n \n \tinit_uart_clk(0);\n@@ -160,12 +53,9 @@ void board_init_f(ulong dummy)\n \n \tpreloader_console_init();\n \n-\t/* Clear the BSS. */\n-\tmemset(__bss_start, 0, __bss_end - __bss_start);\n-\n-\tret = spl_init();\n+\tret = spl_early_init();\n \tif (ret) {\n-\t\tdebug(\"spl_init() failed: %d\\n\", ret);\n+\t\tdebug(\"spl_early_init() failed: %d\\n\", ret);\n \t\thang();\n \t}\n \n@@ -174,5 +64,8 @@ void board_init_f(ulong dummy)\n \t/* DDR initialization */\n \tspl_dram_init();\n \n+\tinit_clk_usdhc(0);\n+\tinit_clk_usdhc(1);\n+\n \tboard_init_r(NULL, 0);\n }\ndiff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig\nindex 4c95363ad07..07354a78629 100644\n--- a/configs/imx8mq_phanbell_defconfig\n+++ b/configs/imx8mq_phanbell_defconfig\n@@ -7,9 +7,6 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y\n CONFIG_SPL_LIBGENERIC_SUPPORT=y\n CONFIG_ENV_SIZE=0x1000\n CONFIG_ENV_OFFSET=0x400000\n-CONFIG_SYS_I2C_MXC_I2C1=y\n-CONFIG_SYS_I2C_MXC_I2C2=y\n-CONFIG_SYS_I2C_MXC_I2C3=y\n CONFIG_DM_GPIO=y\n CONFIG_DEFAULT_DEVICE_TREE=\"imx8mq-phanbell\"\n CONFIG_TARGET_IMX8MQ_PHANBELL=y\n@@ -18,7 +15,7 @@ CONFIG_SYS_MONITOR_LEN=524288\n CONFIG_SPL_MMC=y\n CONFIG_SPL_SERIAL=y\n CONFIG_SPL_DRIVERS_MISC=y\n-CONFIG_SPL_STACK=0x187ff0\n+CONFIG_SPL_STACK=0x920000\n CONFIG_SPL_TEXT_BASE=0x7E1000\n CONFIG_SPL_HAS_BSS_LINKER_SECTION=y\n CONFIG_SPL_BSS_START_ADDR=0x180000\n@@ -67,16 +64,17 @@ CONFIG_CMD_EXT4_WRITE=y\n CONFIG_CMD_FAT=y\n # CONFIG_SPL_DOS_PARTITION is not set\n CONFIG_OF_CONTROL=y\n+CONFIG_SPL_OF_CONTROL=y\n CONFIG_ENV_OVERWRITE=y\n CONFIG_ENV_IS_IN_MMC=y\n CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n CONFIG_ENV_MMC_DEVICE_INDEX=1\n CONFIG_USE_ETHPRIME=y\n CONFIG_ETHPRIME=\"FEC\"\n+CONFIG_SPL_DM=y\n CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000\n CONFIG_MXC_GPIO=y\n CONFIG_DM_I2C=y\n-CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_SUPPORT_EMMC_BOOT=y\n CONFIG_FSL_USDHC=y\n CONFIG_PHYLIB=y\n@@ -84,13 +82,16 @@ CONFIG_PHY_GIGE=y\n CONFIG_FEC_MXC=y\n CONFIG_MII=y\n CONFIG_PINCTRL=y\n+CONFIG_SPL_PINCTRL=y\n CONFIG_PINCTRL_IMX8M=y\n CONFIG_POWER_DOMAIN=y\n CONFIG_IMX8M_POWER_DOMAIN=y\n CONFIG_DM_REGULATOR=y\n CONFIG_DM_REGULATOR_FIXED=y\n CONFIG_DM_REGULATOR_GPIO=y\n-CONFIG_SPL_POWER_I2C=y\n+CONFIG_SPL_DM_REGULATOR=y\n+CONFIG_SPL_DM_REGULATOR_FIXED=y\n+CONFIG_SPL_DM_REGULATOR_GPIO=y\n CONFIG_DM_SERIAL=y\n CONFIG_MXC_UART=y\n CONFIG_DM_THERMAL=y\n", "prefixes": [ "15/15" ] }