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{ "id": 2225420, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225420/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/aebjBidUMEhSpWMw@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<aebjBidUMEhSpWMw@cowardly-lion.the-meissners.org>", "date": "2026-04-21T02:37:58", "name": "GCC 17.0 PowerPC, V6 [PATCH 3/5]: Add support for 512-bit dense math registers.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "860dfe52756efaf6892ff6081485d0554bd3bd0c", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/1.1/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/aebjBidUMEhSpWMw@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 500712, "url": "http://patchwork.ozlabs.org/api/1.1/series/500712/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500712", "date": "2026-04-21T02:37:58", "name": "GCC 17.0 PowerPC, V6 [PATCH 3/5]: Add support for 512-bit dense math registers.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500712/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225420/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225420/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=Xur6g3ml;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1776739086; cv=none;\n b=x49c3C3WpI9D6lnnaGvHZuqW9z3VR6p9idN0SNIBmykxfl6OBiYjbS6v07tsDkt9JotUFCrMHsmzxJwRIxkiIGW20QHiKFKGCMC2i7Hc67WsE3xvEofMKZWQM+vVjx/GunNILew0tak+7eUdt/4S6rs+2M1VH+qI+a+0cDG7Gzk=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776739086; c=relaxed/simple;\n bh=0KhOi3xwp0V1WDNErI9iyLvvDNEQzOcYuZ7+ejvW1Rg=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=qPAJ36mfwxX9ZZKdVSwBCn0Pdy7OQdJL6CEkrxy7Tnb+aHlkg7Pp7rVXPcigqhkIhNOZZ4HbNPmesG5m7cPtrymAjJDRVpAPU7V7hBWswOstLKiCzWv2iPIBQPscMU9PrX6uW3l8/yO3Vb/CcJdmvpmjO6DE5pPsy2Z6j0idqYg=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=Hel0UNmQ1qmUqDpqAct6GYdL4BVkjF\n cH/qfX0nWtYBc=; b=Xur6g3mlEt4Dp2lAGfntBra9yxH8ll9jjjJYqsHRITXwAh\n j/SPb5eD2pxT85/b35S+Jpu37aWBb8oBdN+lESUb8IBYi1BnybUSL7kpHSiXCLwH\n 7unKh7kIrzZaRaefbLyisHjmTwp/0o3uKuXSn8civsNKKxt7d31xdGsVWuMSoLWd\n dHHfcOMjdo2JS0NJLdigDZ4pxYu4Jy0y48nSAusMrNXWiDdRJopZyacUDGaincaE\n dlMJ4VPmjR0WwbY3SgZDIMZxju0/c8Ie3VwXen49BMu67bm7+ecZ2PFc6SKXVsfI\n ETEop39chm18K417Um4POOEfy4Z/lbVqHF7SHoQg==", "Date": "Mon, 20 Apr 2026 22:37:58 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17.0 PowerPC, V6 [PATCH 3/5]: Add support for 512-bit dense math\n registers.", "Message-ID": "<aebjBidUMEhSpWMw@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<aebT1QQbPenBOFeH@cowardly-lion.the-meissners.org>\n <aebfyZbqzSA9YblH@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<aebfyZbqzSA9YblH@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Authority-Analysis": "v=2.4 cv=L78theT8 c=1 sm=1 tr=0 ts=69e6e30c cx=c_pps\n a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=iYQ8MlB5ZGSVG5lEZ4kA:9 a=3ZKOabzyN94A:10 a=CjuIK1q_8ugA:10", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDAyMSBTYWx0ZWRfX1ZOz7zG7dXrv\n ICmHCpIQryNfuAQbbXGSMIxy2/h66N/6fXHwygvZFC3o5iuquf70JxmFR+eO3TS800ibfXkP+aR\n uPrBOArqA0vtsRVCyrasHcBmiq11B07UJ8VS9SgBUziM6wtoZxJ2XFVM1ucVLOlzXfkqXTfqFHl\n sxBCg3X6DcD0cMLNDw8UtpTFx+opNMJndL07j9jpwaQX1f8sTZ9nOS93+nFyG/PMzm8xtJDdJnz\n HRxhsEjxnmlZK/mx82V/XtE2akOLu7gFxAQw8DgLgTWWgh7yml+Xbv3dw37Adcx4h5MTIrzWB64\n iQW1XsKhDOqcM9V6jd0yzFUjyqg3j51gGuc0y5BTxjnUF5d9HdWYUutnIZx4vWEu54tUXUYli7/\n q991nTwZk0KkpLb+YZqZi61YzIkASrOvmpJz9nNzKAWUB0yDn3oIcCJU1+cx0DvAkgi6T2RRPGq\n SDb8v+xl0DEy37aWqcg==", "X-Proofpoint-GUID": "_fUl32Dxps2LCIeZNJCMZAL2uZRemqOr", "X-Proofpoint-ORIG-GUID": "_fUl32Dxps2LCIeZNJCMZAL2uZRemqOr", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0\n lowpriorityscore=0 adultscore=0 clxscore=1015 malwarescore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210021", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "This patch adds basic support for dense math registers. It includes support for\nmoving values to/from dense registers. The MMA instructions are not yet\nmodified to know about dense math registers. The -mcpu=future option does not\nset -mdense-math in this patch. A future patch will make these changes.\n\nThe changes from the V3 patches include:\n\n 1:\tXOmode moves include moving to/from dense math registers.\n\n 2:\tAdd predicate dense_math_operand.\n\n 3:\tMake the predicate accumulator_operand match on dense math registers.\n\n 4:\tAdd dense math register class.\n\n 5:\tAdd the 8 dense math register accumulators with internal register\n\tnumbers 111-118.\n\n 6:\tMake the 'wD' constraint match dense math register if -mdense-math, and\n\t4 adjacent VSX register if -mno-dense-math is in effect.\n\n 7:\tSet up the reload information so that the register allocator knows that\n\tdense math registers do not have load or store instructions. Instead to\n\tread/write dense math registers, you have to use VSX registers as\n\tintermediaries.\n\n 8:\tMake the print_operand '%A' output operand now knows about accumulators\n\tin dense math registrs and accumulators in 4 adjacent VSX registers.\n\n 9:\tUpdate register move and memmory load/store costs for dense math\n\tregisters.\n\n 10:\tMake dense math registers a pressure class for register allocation.\n\n 11:\tDo not issue MMA deprime instructions if -mdense-math is in effect.\n\n 12:\tAdd support for dense math registers to rs6000_split_multireg_move.\n\nThe changes from V4 patches include:\n\n 1:\tUse the new TARGET_MMA_DENSE_MATH and TARGET_MMA_NO_DENSE_MATH macros\n\tin the compiler.\n\n 2:\tAllow XOmode mode to be used if the user did -mno-mma -mcpu=future.\n\nNote, in the intro mail message, I said that this was V4 of the\npatches, but I missed I had submitted V5 on February 21st, 2026, so\nthis is now V6:\n\nThis is version 6 of the patches (which is the same as version 5).\nVersion 5 patches are at:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708943.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708944.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708945.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708946.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708947.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-February/708948.html\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\ngcc/\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\n\t* config/rs6000/mma.md (movxo): Convert to being a define_expand that\n\tcan handle both the original MMA support without dense math registes,\n\tand adding dense math support.\n\t(movxo_nodm): Rename original movxo insn, and restrict this insn to when\n\twe do not have dense math registers.\n\t(movxo_dm): New define_insn_and_split for dense math registers.\n\t* config/rs6000/predicates.md (dense_math_operand): New predicate.\n\t(accumulator_operand): Add support for dense math registes.\n\t* config/rs6000/rs6000.cc (enum rs6000_reg_type): Add dense math\n\tregister support.\n\t(enum rs6000_reload_reg_typ): Likewise.\n\t(LAST_RELOAD_REG_CLASS): Likewise.\n\t(reload_reg_map): Likewise.\n\t(rs6000_reg_names): Likewise.\n\t(alt_reg_names): Likewise.\n\t(rs6000_hard_regno_nregs_internal): Likewise.\n\t(rs6000_hard_regno_mode_ok_uncached): Likewise.\n\t(rs6000_debug_reg_global): Likewise.\n\t(rs6000_setup_reg_addr_masks): Likewise.\n\t(rs6000_init_hard_regno_mode_ok): Likewise.\n\t(rs6000_option_override_internal): Likewise.\n\t(rs6000_secondary_reload_memory): Likewise.\n\t(rs6000_secondary_reload_simple_move): Likewise.\n\t(rs6000_preferred_reload_class): Likewise.\n\t(rs6000_secondary_reload_class): Likewise.\n\t(print_operand): Likewise.\n\t(rs6000_dense_math_register_move_cost): New helper function.\n\t(rs6000_register_move_cost): Add dense math register support.\n\t(rs6000_memory_move_cost): Likewise.\n\t(rs6000_compute_pressure_classes): Likewise.\n\t(rs6000_debugger_regno): Likewise.\n\t(rs6000_opt_masks): Likewise.\n\t(rs6000_split_multireg_move): Likewise.\n\t* config/rs6000/rs6000.h (UNITS_PER_DM_WORD): New macro.\n\t(FIRST_PSEUDO_REGISTER): Add dense math register support.\n\t(FIXED_REGISTERS): Likewise.\n\t(CALL_REALLY_USED_REGISTERS): Likewise.\n\t(REG_ALLOC_ORDER): Likewise.\n\t(DM_REGNO_P): New macro.\n\t(enum reg_class): Add dense math register support.\n\t(REG_CLASS_NAMES): Likewise.\n\t(REGISTER_NAMES): Likewise.\n\t(ADDITIONAL_REGISTER_NAMES): Likewise.\n\t* config/rs6000/rs6000.md (FIRST_DM_REGNO): New constant.\n\t(LAST_DM_REGNO): Likewise.\n---\n gcc/config/rs6000/mma.md | 39 +++++-\n gcc/config/rs6000/predicates.md | 29 ++++-\n gcc/config/rs6000/rs6000.cc | 214 ++++++++++++++++++++++++++------\n gcc/config/rs6000/rs6000.h | 37 +++++-\n gcc/config/rs6000/rs6000.md | 2 +\n 5 files changed, 268 insertions(+), 53 deletions(-)", "diff": "diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md\nindex 1103f1fc037..c1e16bf2957 100644\n--- a/gcc/config/rs6000/mma.md\n+++ b/gcc/config/rs6000/mma.md\n@@ -314,13 +314,13 @@ (define_insn_and_split \"*movoo\"\n (set_attr \"length\" \"*,*,8\")])\n \n \f\n-;; Vector quad support. XOmode can only live in FPRs.\n+;; Vector quad support.\n (define_expand \"movxo\"\n [(set (match_operand:XO 0 \"nonimmediate_operand\")\n \t(match_operand:XO 1 \"input_operand\"))]\n \"\"\n {\n- if (TARGET_MMA)\n+ if (TARGET_MMA || TARGET_DENSE_MATH)\n {\n rs6000_emit_move (operands[0], operands[1], XOmode);\n DONE;\n@@ -339,10 +339,13 @@ (define_expand \"movxo\"\n gcc_assert (false);\n })\n \n-(define_insn_and_split \"*movxo\"\n+;; If we do not have dense math registers, XOmode can only live in FPR\n+;; registers (0..31).\n+\n+(define_insn_and_split \"*movxo_nodm\"\n [(set (match_operand:XO 0 \"nonimmediate_operand\" \"=d,ZwO,d\")\n \t(match_operand:XO 1 \"input_operand\" \"ZwO,d,d\"))]\n- \"TARGET_MMA\n+ \"TARGET_MMA_NO_DENSE_MATH\n && (gpc_reg_operand (operands[0], XOmode)\n || gpc_reg_operand (operands[1], XOmode))\"\n \"@\n@@ -359,6 +362,34 @@ (define_insn_and_split \"*movxo\"\n (set_attr \"length\" \"*,*,16\")\n (set_attr \"max_prefixed_insns\" \"2,2,*\")])\n \n+;; If dense math registers are available, XOmode can live in either VSX\n+;; registers (0..63) or dense math registers.\n+\n+(define_insn_and_split \"*movxo_dm\"\n+ [(set (match_operand:XO 0 \"nonimmediate_operand\" \"=wa,ZwO,wa,wD,wD,wa\")\n+\t(match_operand:XO 1 \"input_operand\" \"ZwO,wa, wa,wa,wD,wD\"))]\n+ \"TARGET_DENSE_MATH\n+ && (gpc_reg_operand (operands[0], XOmode)\n+ || gpc_reg_operand (operands[1], XOmode))\"\n+ \"@\n+ #\n+ #\n+ #\n+ dmxxinstdmr512 %0,%1,%Y1,0\n+ dmmr %0,%1\n+ dmxxextfdmr512 %0,%Y0,%1,0\"\n+ \"&& reload_completed\n+ && !dense_math_operand (operands[0], XOmode)\n+ && !dense_math_operand (operands[1], XOmode)\"\n+ [(const_int 0)]\n+{\n+ rs6000_split_multireg_move (operands[0], operands[1]);\n+ DONE;\n+}\n+ [(set_attr \"type\" \"vecload,vecstore,veclogical,mma,mma,mma\")\n+ (set_attr \"length\" \"*,*,16,*,*,*\")\n+ (set_attr \"max_prefixed_insns\" \"2,2,*,*,*,*\")])\n+\n (define_expand \"vsx_assemble_pair\"\n [(match_operand:OO 0 \"vsx_register_operand\")\n (match_operand:V16QI 1 \"mma_assemble_input_operand\")\ndiff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md\nindex 682fd2dc6e8..8221e0fa2d0 100644\n--- a/gcc/config/rs6000/predicates.md\n+++ b/gcc/config/rs6000/predicates.md\n@@ -186,8 +186,29 @@ (define_predicate \"vlogical_operand\"\n return VLOGICAL_REGNO_P (REGNO (op));\n })\n \n-;; Return 1 if op is an accumulator. On power10 systems, the accumulators\n-;; overlap with the FPRs.\n+;; Return 1 if op is a dense math register\n+(define_predicate \"dense_math_operand\"\n+ (match_operand 0 \"register_operand\")\n+{\n+ if (!TARGET_DENSE_MATH)\n+ return 0;\n+\n+ if (!REG_P (op))\n+ return 0;\n+\n+ if (!HARD_REGISTER_P (op))\n+ return 1;\n+\n+ return DM_REGNO_P (REGNO (op));\n+})\n+\n+;; Return 1 if op is an accumulator.\n+;;\n+;; On power10 and power11 systems, the accumulators overlap with the\n+;; FPRs and the register must be divisible by 4.\n+;;\n+;; On systems with dense math registers, the accumulators are separate\n+;; registers and do not overlap with the FPR registers.\n (define_predicate \"accumulator_operand\"\n (match_operand 0 \"register_operand\")\n {\n@@ -201,7 +222,9 @@ (define_predicate \"accumulator_operand\"\n return 1;\n \n int r = REGNO (op);\n- return FP_REGNO_P (r) && (r & 3) == 0;\n+ return (TARGET_DENSE_MATH\n+\t ? DM_REGNO_P (r)\n+\t : FP_REGNO_P (r) && (r & 3) == 0);\n })\n \n ;; Return 1 if op is the carry register.\ndiff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc\nindex f5ba84a108e..33700082812 100644\n--- a/gcc/config/rs6000/rs6000.cc\n+++ b/gcc/config/rs6000/rs6000.cc\n@@ -292,7 +292,8 @@ enum rs6000_reg_type {\n ALTIVEC_REG_TYPE,\n FPR_REG_TYPE,\n SPR_REG_TYPE,\n- CR_REG_TYPE\n+ CR_REG_TYPE,\n+ DM_REG_TYPE\n };\n \n /* Map register class to register type. */\n@@ -306,22 +307,24 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];\n \n \n /* Register classes we care about in secondary reload or go if legitimate\n- address. We only need to worry about GPR, FPR, and Altivec registers here,\n- along an ANY field that is the OR of the 3 register classes. */\n+ address. We only need to worry about GPR, FPR, Altivec, and dense math\n+ registers here, along an ANY field that is the OR of the 4 register\n+ classes. */\n \n enum rs6000_reload_reg_type {\n RELOAD_REG_GPR,\t\t\t/* General purpose registers. */\n RELOAD_REG_FPR,\t\t\t/* Traditional floating point regs. */\n RELOAD_REG_VMX,\t\t\t/* Altivec (VMX) registers. */\n- RELOAD_REG_ANY,\t\t\t/* OR of GPR, FPR, Altivec masks. */\n+ RELOAD_REG_DMR,\t\t\t/* Dense math registers. */\n+ RELOAD_REG_ANY,\t\t\t/* OR of GPR/FPR/VMX/DMR masks. */\n N_RELOAD_REG\n };\n \n-/* For setting up register classes, loop through the 3 register classes mapping\n+/* For setting up register classes, loop through the 4 register classes mapping\n into real registers, and skip the ANY class, which is just an OR of the\n bits. */\n #define FIRST_RELOAD_REG_CLASS\tRELOAD_REG_GPR\n-#define LAST_RELOAD_REG_CLASS\tRELOAD_REG_VMX\n+#define LAST_RELOAD_REG_CLASS\tRELOAD_REG_DMR\n \n /* Map reload register type to a register in the register class. */\n struct reload_reg_map_type {\n@@ -333,6 +336,7 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {\n { \"Gpr\",\tFIRST_GPR_REGNO },\t/* RELOAD_REG_GPR. */\n { \"Fpr\",\tFIRST_FPR_REGNO },\t/* RELOAD_REG_FPR. */\n { \"VMX\",\tFIRST_ALTIVEC_REGNO },\t/* RELOAD_REG_VMX. */\n+ { \"Dmr\",\tFIRST_DM_REGNO },\t/* RELOAD_REG_DMR. */\n { \"Any\",\t-1 },\t\t\t/* RELOAD_REG_ANY. */\n };\n \n@@ -1226,6 +1230,8 @@ char rs6000_reg_names[][8] =\n \"0\", \"1\", \"2\", \"3\", \"4\", \"5\", \"6\", \"7\",\n /* vrsave vscr sfp */\n \"vrsave\", \"vscr\", \"sfp\",\n+ /* dense math registers. */\n+ \"0\", \"1\", \"2\", \"3\", \"4\", \"5\", \"6\", \"7\",\n };\n \n #ifdef TARGET_REGNAMES\n@@ -1252,6 +1258,8 @@ static const char alt_reg_names[][8] =\n \"%cr0\", \"%cr1\", \"%cr2\", \"%cr3\", \"%cr4\", \"%cr5\", \"%cr6\", \"%cr7\",\n /* vrsave vscr sfp */\n \"vrsave\", \"vscr\", \"sfp\",\n+ /* dense math registers. */\n+ \"%dmr0\", \"%dmr1\", \"%dmr2\", \"%dmr3\", \"%dmr4\", \"%dmr5\", \"%dmr6\", \"%dmr7\",\n };\n #endif\n \n@@ -1842,6 +1850,9 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)\n else if (ALTIVEC_REGNO_P (regno))\n reg_size = UNITS_PER_ALTIVEC_WORD;\n \n+ else if (DM_REGNO_P (regno))\n+ reg_size = UNITS_PER_DM_WORD;\n+\n else\n reg_size = UNITS_PER_WORD;\n \n@@ -1863,9 +1874,32 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)\n if (mode == OOmode)\n return (TARGET_MMA && VSX_REGNO_P (regno) && (regno & 1) == 0);\n \n- /* MMA accumulator modes need FPR registers divisible by 4. */\n+ /* On ISA 3.1 (power10), MMA accumulator modes need FPR registers divisible\n+ by 4.\n+\n+ If dense math registers are enabled, we can allow all VSX registers plus\n+ the dense math registers. VSX registers are used to load and store the\n+ registers as the accumulator registers do not have load and store\n+ instructions. Because we just use the VSX registers for load/store\n+ operations, we just need to make sure load vector pair and store vector\n+ pair instructions can be used. */\n if (mode == XOmode)\n- return (TARGET_MMA && FP_REGNO_P (regno) && (regno & 3) == 0);\n+ {\n+ if (!TARGET_DENSE_MATH)\n+\treturn (FP_REGNO_P (regno) && (regno & 3) == 0);\n+\n+ else if (DM_REGNO_P (regno))\n+\treturn 1;\n+\n+ else\n+\treturn (VSX_REGNO_P (regno)\n+\t\t&& VSX_REGNO_P (last_regno)\n+\t\t&& (regno & 1) == 0);\n+ }\n+\n+ /* No other types other than XOmode can go in dense math registers. */\n+ if (DM_REGNO_P (regno))\n+ return 0;\n \n /* PTImode can only go in GPRs. Quad word memory operations require even/odd\n register combinations, and use PTImode where we need to deal with quad\n@@ -2308,6 +2342,7 @@ rs6000_debug_reg_global (void)\n rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,\n \t\t\t LAST_ALTIVEC_REGNO,\n \t\t\t \"vs\");\n+ rs6000_debug_reg_print (FIRST_DM_REGNO, LAST_DM_REGNO, \"dense_math\");\n rs6000_debug_reg_print (LR_REGNO, LR_REGNO, \"lr\");\n rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, \"ctr\");\n rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, \"cr\");\n@@ -2634,6 +2669,21 @@ rs6000_setup_reg_addr_masks (void)\n \t addr_mask = 0;\n \t reg = reload_reg_map[rc].reg;\n \n+\t /* Special case dense math registers. */\n+\t if (rc == RELOAD_REG_DMR)\n+\t {\n+\t if (TARGET_DENSE_MATH && m2 == XOmode)\n+\t\t{\n+\t\t addr_mask = RELOAD_REG_VALID;\n+\t\t reg_addr[m].addr_mask[rc] = addr_mask;\n+\t\t any_addr_mask |= addr_mask;\n+\t\t}\n+\t else\n+\t\treg_addr[m].addr_mask[rc] = 0;\n+\n+\t continue;\n+\t }\n+\n \t /* Can mode values go in the GPR/FPR/Altivec registers? */\n \t if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])\n \t {\n@@ -2784,6 +2834,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)\n for (r = CR1_REGNO; r <= CR7_REGNO; ++r)\n rs6000_regno_regclass[r] = CR_REGS;\n \n+ for (r = FIRST_DM_REGNO; r <= LAST_DM_REGNO; ++r)\n+ rs6000_regno_regclass[r] = DM_REGS;\n+\n rs6000_regno_regclass[LR_REGNO] = LINK_REGS;\n rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;\n rs6000_regno_regclass[CA_REGNO] = NO_REGS;\n@@ -2808,6 +2861,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)\n reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;\n reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;\n reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;\n+ reg_class_to_reg_type[(int)DM_REGS] = DM_REG_TYPE;\n \n if (TARGET_VSX)\n {\n@@ -2994,8 +3048,12 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)\n if (TARGET_DIRECT_MOVE_128)\n rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;\n \n- if (TARGET_MMA)\n+ /* Support for the accumulator registers, either FPR registers (aka original\n+ mma) or dense math registers. */\n+ if (TARGET_MMA_NO_DENSE_MATH)\n rs6000_constraints[RS6000_CONSTRAINT_wD] = FLOAT_REGS;\n+ else if (TARGET_MMA_DENSE_MATH)\n+ rs6000_constraints[RS6000_CONSTRAINT_wD] = DM_REGS;\n \n /* Set up the reload helper and direct move functions. */\n if (TARGET_VSX || TARGET_ALTIVEC)\n@@ -12365,6 +12423,11 @@ rs6000_secondary_reload_memory (rtx addr,\n addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]\n \t\t & ~RELOAD_REG_AND_M16);\n \n+ /* Dense math registers use VSX registers for memory operations, and need to\n+ generate some extra instructions. */\n+ else if (rclass == DM_REGS)\n+ return 2;\n+\n /* If the register allocator hasn't made up its mind yet on the register\n class to use, settle on defaults to use. */\n else if (rclass == NO_REGS)\n@@ -12693,6 +12756,13 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,\n \t || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))\n return true;\n \n+ /* We can transfer between VSX registers and dense math registers without\n+ needing extra registers. */\n+ if (TARGET_DENSE_MATH && mode == XOmode\n+ && ((to_type == DM_REG_TYPE && from_type == VSX_REG_TYPE)\n+\t || (to_type == VSX_REG_TYPE && from_type == DM_REG_TYPE)))\n+ return true;\n+\n return false;\n }\n \n@@ -13387,6 +13457,10 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)\n machine_mode mode = GET_MODE (x);\n bool is_constant = CONSTANT_P (x);\n \n+ /* Dense math registers can't be loaded or stored. */\n+ if (rclass == DM_REGS)\n+ return NO_REGS;\n+\n /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred\n reload class for it. */\n if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)\n@@ -13483,7 +13557,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)\n \treturn VSX_REGS;\n \n if (mode == XOmode)\n-\treturn FLOAT_REGS;\n+\treturn TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS;\n \n if (GET_MODE_CLASS (mode) == MODE_INT)\n \treturn GENERAL_REGS;\n@@ -13608,6 +13682,11 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,\n else\n regno = -1;\n \n+ /* Dense math registers don't have loads or stores. We have to go through\n+ the VSX registers to load XOmode (vector quad). */\n+ if (TARGET_DENSE_MATH && rclass == DM_REGS)\n+ return VSX_REGS;\n+\n /* If we have VSX register moves, prefer moving scalar values between\n Altivec registers and GPR by going via an FPR (and then via memory)\n instead of reloading the secondary memory address for Altivec moves. */\n@@ -14139,8 +14218,14 @@ print_operand (FILE *file, rtx x, int code)\n \t output_operand. */\n \n case 'A':\n- /* Write the MMA accumulator number associated with VSX register X. */\n- if (!REG_P (x) || !FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)\n+ /* Write the MMA accumulator number associated with VSX register X. On\n+\t dense math systems, only allow dense math accumulators, not\n+\t accumulators overlapping with the FPR registers. */\n+ if (!REG_P (x))\n+\toutput_operand_lossage (\"invalid %%A value\");\n+ else if (TARGET_DENSE_MATH && DM_REGNO_P (REGNO (x)))\n+\tfprintf (file, \"%d\", REGNO (x) - FIRST_DM_REGNO);\n+ else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)\n \toutput_operand_lossage (\"invalid %%A value\");\n else\n \tfprintf (file, \"%d\", (REGNO (x) - FIRST_FPR_REGNO) / 4);\n@@ -22760,6 +22845,31 @@ rs6000_debug_address_cost (rtx x, machine_mode mode,\n }\n \n \n+/* Subroutine to determine the move cost of dense math registers. If we are\n+ moving to/from VSX_REGISTER registers, the cost is either 1 move (for\n+ 512-bit accumulators) or 2 moves (for 1,024 dense math registers). If we are\n+ moving to anything else like GPR registers, make the cost very high. */\n+\n+static int\n+rs6000_dense_math_register_move_cost (machine_mode mode, reg_class_t rclass)\n+{\n+ const int reg_move_base = 2;\n+ HARD_REG_SET vsx_set = (reg_class_contents[rclass]\n+\t\t\t & reg_class_contents[VSX_REGS]);\n+\n+ if (TARGET_DENSE_MATH && !hard_reg_set_empty_p (vsx_set))\n+ {\n+ /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */\n+ if (mode == XOmode)\n+\treturn reg_move_base;\n+\n+ else\n+\treturn reg_move_base * 2 * hard_regno_nregs (FIRST_DM_REGNO, mode);\n+ }\n+\n+ return 1000 * 2 * hard_regno_nregs (FIRST_DM_REGNO, mode);\n+}\n+\n /* A C expression returning the cost of moving data from a register of class\n CLASS1 to one of CLASS2. */\n \n@@ -22773,17 +22883,28 @@ rs6000_register_move_cost (machine_mode mode,\n if (TARGET_DEBUG_COST)\n dbg_cost_ctrl++;\n \n+ HARD_REG_SET to_vsx, from_vsx;\n+ to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];\n+ from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];\n+\n+ /* Special case dense math registers, that can only move to/from VSX registers. */\n+ if (from == DM_REGS && to == DM_REGS)\n+ ret = 2 * hard_regno_nregs (FIRST_DM_REGNO, mode);\n+\n+ else if (from == DM_REGS)\n+ ret = rs6000_dense_math_register_move_cost (mode, to);\n+\n+ else if (to == DM_REGS)\n+ ret = rs6000_dense_math_register_move_cost (mode, from);\n+\n /* If we have VSX, we can easily move between FPR or Altivec registers,\n otherwise we can only easily move within classes.\n Do this first so we give best-case answers for union classes\n containing both gprs and vsx regs. */\n- HARD_REG_SET to_vsx, from_vsx;\n- to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];\n- from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];\n- if (!hard_reg_set_empty_p (to_vsx)\n- && !hard_reg_set_empty_p (from_vsx)\n- && (TARGET_VSX\n-\t || hard_reg_set_intersect_p (to_vsx, from_vsx)))\n+ else if (!hard_reg_set_empty_p (to_vsx)\n+\t && !hard_reg_set_empty_p (from_vsx)\n+\t && (TARGET_VSX\n+\t || hard_reg_set_intersect_p (to_vsx, from_vsx)))\n {\n int reg = FIRST_FPR_REGNO;\n if (TARGET_VSX\n@@ -22879,6 +23000,9 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,\n ret = 4 * hard_regno_nregs (32, mode);\n else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))\n ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);\n+ else if (reg_classes_intersect_p (rclass, DM_REGS))\n+ ret = (rs6000_dense_math_register_move_cost (mode, VSX_REGS)\n+\t + rs6000_memory_move_cost (mode, VSX_REGS, false));\n else\n ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);\n \n@@ -24087,6 +24211,8 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes)\n if (TARGET_HARD_FLOAT)\n \tpressure_classes[n++] = FLOAT_REGS;\n }\n+ if (TARGET_DENSE_MATH)\n+ pressure_classes[n++] = DM_REGS;\n pressure_classes[n++] = CR_REGS;\n pressure_classes[n++] = SPECIAL_REGS;\n \n@@ -24251,6 +24377,10 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format)\n return 67;\n if (regno == 64)\n return 64;\n+ /* XXX: This is a guess. The GCC register number for FIRST_DM_REGNO is 111,\n+ but the frame pointer regnum uses that. */\n+ if (DM_REGNO_P (regno))\n+ return regno - FIRST_DM_REGNO + 112;\n \n gcc_unreachable ();\n }\n@@ -27490,9 +27620,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t unsigned offset = 0;\n \t unsigned size = GET_MODE_SIZE (reg_mode);\n \n-\t /* If we are reading an accumulator register, we have to\n-\t deprime it before we can access it. */\n-\t if (TARGET_MMA\n+\t /* If we are reading an accumulator register, we have to deprime it\n+\t before we can access it unless we have dense math registers. */\n+\t if (TARGET_MMA_NO_DENSE_MATH\n \t && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))\n \t emit_insn (gen_mma_xxmfacc (src, src));\n \n@@ -27524,9 +27654,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t emit_insn (gen_rtx_SET (dst2, src2));\n \t }\n \n-\t /* If we are writing an accumulator register, we have to\n-\t prime it after we've written it. */\n-\t if (TARGET_MMA\n+\t /* If we are writing an accumulator register, we have to prime it\n+\t after we've written it unless we have dense math registers. */\n+\t if (TARGET_MMA_NO_DENSE_MATH\n \t && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))\n \t emit_insn (gen_mma_xxmtacc (dst, dst));\n \n@@ -27540,7 +27670,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t\t || XINT (src, 1) == UNSPECV_MMA_ASSEMBLE);\n \t gcc_assert (REG_P (dst));\n \t if (GET_MODE (src) == XOmode)\n-\t gcc_assert (FP_REGNO_P (REGNO (dst)));\n+\t gcc_assert ((TARGET_DENSE_MATH\n+\t\t\t ? VSX_REGNO_P (REGNO (dst))\n+\t\t\t : FP_REGNO_P (REGNO (dst))));\n \t if (GET_MODE (src) == OOmode)\n \t gcc_assert (VSX_REGNO_P (REGNO (dst)));\n \n@@ -27593,9 +27725,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t emit_insn (gen_rtx_SET (dst_i, op));\n \t }\n \n-\t /* We are writing an accumulator register, so we have to\n-\t prime it after we've written it. */\n-\t if (GET_MODE (src) == XOmode)\n+\t /* We are writing an accumulator register, so we have to prime it\n+\t after we've written it unless we have dense math registers. */\n+\t if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH)\n \t emit_insn (gen_mma_xxmtacc (dst, dst));\n \n \t return;\n@@ -27606,9 +27738,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \n if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))\n {\n- /* If we are reading an accumulator register, we have to\n-\t deprime it before we can access it. */\n- if (TARGET_MMA\n+ /* If we are reading an accumulator register, we have to deprime it\n+\t before we can access it unless we have dense math registers. */\n+ if (TARGET_MMA_NO_DENSE_MATH\n \t && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))\n \temit_insn (gen_mma_xxmfacc (src, src));\n \n@@ -27634,9 +27766,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t\t\t\t\t\t\t i * reg_mode_size)));\n \t}\n \n- /* If we are writing an accumulator register, we have to\n-\t prime it after we've written it. */\n- if (TARGET_MMA\n+ /* If we are writing an accumulator register, we have to prime it after\n+\t we've written it unless we have dense math registers. */\n+ if (TARGET_MMA_NO_DENSE_MATH\n \t && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))\n \temit_insn (gen_mma_xxmtacc (dst, dst));\n }\n@@ -27771,9 +27903,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));\n \t}\n \n- /* If we are reading an accumulator register, we have to\n-\t deprime it before we can access it. */\n- if (TARGET_MMA && REG_P (src)\n+ /* If we are reading an accumulator register, we have to deprime it\n+\t before we can access it unless we have dense math registers. */\n+ if (TARGET_MMA_NO_DENSE_MATH && REG_P (src)\n \t && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src)))\n \temit_insn (gen_mma_xxmfacc (src, src));\n \n@@ -27803,9 +27935,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)\n \t\t\t\t\t\t\t j * reg_mode_size)));\n \t}\n \n- /* If we are writing an accumulator register, we have to\n-\t prime it after we've written it. */\n- if (TARGET_MMA && REG_P (dst)\n+ /* If we are writing an accumulator register, we have to prime it after\n+\t we've written it unless we have dense math registers. */\n+ if (TARGET_MMA_NO_DENSE_MATH && REG_P (dst)\n \t && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst)))\n \temit_insn (gen_mma_xxmtacc (dst, dst));\n \ndiff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h\nindex 91e60085515..0fbfeb9c73e 100644\n--- a/gcc/config/rs6000/rs6000.h\n+++ b/gcc/config/rs6000/rs6000.h\n@@ -659,6 +659,7 @@ extern unsigned char rs6000_recip_bits[];\n #define UNITS_PER_FP_WORD 8\n #define UNITS_PER_ALTIVEC_WORD 16\n #define UNITS_PER_VSX_WORD 16\n+#define UNITS_PER_DM_WORD 128\n \n /* Type used for ptrdiff_t, as a string used in a declaration. */\n #define PTRDIFF_TYPE \"int\"\n@@ -772,7 +773,7 @@ enum data_align { align_abi, align_opt, align_both };\n Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame\n pointer, which is eventually eliminated in favor of SP or FP. */\n \n-#define FIRST_PSEUDO_REGISTER 111\n+#define FIRST_PSEUDO_REGISTER 119\n \n /* Use standard DWARF numbering for DWARF debugging information. */\n #define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)\n@@ -809,7 +810,9 @@ enum data_align { align_abi, align_opt, align_both };\n /* cr0..cr7 */\t\t\t\t \\\n 0, 0, 0, 0, 0, 0, 0, 0,\t\t\t \\\n /* vrsave vscr sfp */\t\t\t \\\n- 1, 1, 1\t\t\t\t\t \\\n+ 1, 1, 1,\t\t\t\t\t \\\n+ /* Dense math registers. */\t\t\t \\\n+ 0, 0, 0, 0, 0, 0, 0, 0\t\t\t \\\n }\n \n /* Like `CALL_USED_REGISTERS' except this macro doesn't require that\n@@ -833,7 +836,9 @@ enum data_align { align_abi, align_opt, align_both };\n /* cr0..cr7 */\t\t\t\t \\\n 1, 1, 0, 0, 0, 1, 1, 1,\t\t\t \\\n /* vrsave vscr sfp */\t\t\t \\\n- 0, 0, 0\t\t\t\t\t \\\n+ 0, 0, 0,\t\t\t\t\t \\\n+ /* Dense math registers. */\t\t\t \\\n+ 0, 0, 0, 0, 0, 0, 0, 0\t\t\t \\\n }\n \n #define TOTAL_ALTIVEC_REGS\t(LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)\n@@ -870,6 +875,7 @@ enum data_align { align_abi, align_opt, align_both };\n \tv2\t\t(not saved; incoming vector arg reg; return value)\n \tv19 - v14\t(not saved or used for anything)\n \tv31 - v20\t(saved; order given to save least number)\n+\tdmr0 - dmr7\t(not saved)\n \tvrsave, vscr\t(fixed)\n \tsfp\t\t(fixed)\n */\n@@ -912,6 +918,9 @@ enum data_align { align_abi, align_opt, align_both };\n 66,\t\t\t\t\t\t\t\t\\\n 83, 82, 81, 80, 79, 78,\t\t\t\t\t\\\n 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84,\t\t\\\n+ /* Dense math registers. */\t\t\t\t\t\\\n+ 111, 112, 113, 114, 115, 116, 117, 118,\t\t\t\\\n+ /* Vrsave, vscr, sfp. */\t\t\t\t\t\\\n 108, 109,\t\t\t\t\t\t\t\\\n 110\t\t\t\t\t\t\t\t\\\n }\n@@ -938,6 +947,9 @@ enum data_align { align_abi, align_opt, align_both };\n /* True if register is a VSX register. */\n #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))\n \n+/* True if register is a Dense math register. */\n+#define DM_REGNO_P(N)\t((N) >= FIRST_DM_REGNO && (N) <= LAST_DM_REGNO)\n+\n /* Alternate name for any vector register supporting floating point, no matter\n which instruction set(s) are available. */\n #define VFLOAT_REGNO_P(N) \\\n@@ -1075,6 +1087,7 @@ enum reg_class\n FLOAT_REGS,\n ALTIVEC_REGS,\n VSX_REGS,\n+ DM_REGS,\n VRSAVE_REGS,\n VSCR_REGS,\n GEN_OR_FLOAT_REGS,\n@@ -1104,6 +1117,7 @@ enum reg_class\n \"FLOAT_REGS\",\t\t\t\t\t\t\t\t\\\n \"ALTIVEC_REGS\",\t\t\t\t\t\t\t\\\n \"VSX_REGS\",\t\t\t\t\t\t\t\t\\\n+ \"DM_REGS\",\t\t\t\t\t\t\t\t\\\n \"VRSAVE_REGS\",\t\t\t\t\t\t\t\\\n \"VSCR_REGS\",\t\t\t\t\t\t\t\t\\\n \"GEN_OR_FLOAT_REGS\",\t\t\t\t\t\t\t\\\n@@ -1138,6 +1152,8 @@ enum reg_class\n { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 },\t\t\t\\\n /* VSX_REGS. */\t\t\t\t\t\t\t\\\n { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 },\t\t\t\\\n+ /* DM_REGS. */\t\t\t\t\t\t\t\\\n+ { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 },\t\t\t\\\n /* VRSAVE_REGS. */\t\t\t\t\t\t\t\\\n { 0x00000000, 0x00000000, 0x00000000, 0x00001000 },\t\t\t\\\n /* VSCR_REGS. */\t\t\t\t\t\t\t\\\n@@ -1165,7 +1181,7 @@ enum reg_class\n /* CA_REGS. */\t\t\t\t\t\t\t\\\n { 0x00000000, 0x00000000, 0x00000000, 0x00000004 },\t\t\t\\\n /* ALL_REGS. */\t\t\t\t\t\t\t\\\n- { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff }\t\t\t\\\n+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x007fffff }\t\t\t\\\n }\n \n /* The same information, inverted:\n@@ -2066,7 +2082,16 @@ extern char rs6000_reg_names[][8];\t/* register names (0 vs. %r0). */\n &rs6000_reg_names[108][0],\t/* vrsave */\t\t\t\t\\\n &rs6000_reg_names[109][0],\t/* vscr */\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n- &rs6000_reg_names[110][0]\t/* sfp */\t\t\t\t\\\n+ &rs6000_reg_names[110][0],\t/* sfp */\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ &rs6000_reg_names[111][0],\t/* dmr0 */\t\t\t\t\\\n+ &rs6000_reg_names[112][0],\t/* dmr1 */\t\t\t\t\\\n+ &rs6000_reg_names[113][0],\t/* dmr2 */\t\t\t\t\\\n+ &rs6000_reg_names[114][0],\t/* dmr3 */\t\t\t\t\\\n+ &rs6000_reg_names[115][0],\t/* dmr4 */\t\t\t\t\\\n+ &rs6000_reg_names[116][0],\t/* dmr5 */\t\t\t\t\\\n+ &rs6000_reg_names[117][0],\t/* dmr6 */\t\t\t\t\\\n+ &rs6000_reg_names[118][0],\t/* dmr7 */\t\t\t\t\\\n }\n \n /* Table of additional register names to use in user input. */\n@@ -2120,6 +2145,8 @@ extern char rs6000_reg_names[][8];\t/* register names (0 vs. %r0). */\n {\"vs52\", 84}, {\"vs53\", 85}, {\"vs54\", 86}, {\"vs55\", 87},\t\\\n {\"vs56\", 88}, {\"vs57\", 89}, {\"vs58\", 90}, {\"vs59\", 91},\t\\\n {\"vs60\", 92}, {\"vs61\", 93}, {\"vs62\", 94}, {\"vs63\", 95},\t\\\n+ {\"dmr0\", 111}, {\"dmr1\", 112}, {\"dmr2\", 113}, {\"dmr3\", 114},\t\\\n+ {\"dmr4\", 115}, {\"dmr5\", 116}, {\"dmr6\", 117}, {\"dmr7\", 118},\t\\\n }\n \n /* This is how to output an element of a case-vector that is relative. */\ndiff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\nindex 3089551552c..57a239791ee 100644\n--- a/gcc/config/rs6000/rs6000.md\n+++ b/gcc/config/rs6000/rs6000.md\n@@ -51,6 +51,8 @@ (define_constants\n (VRSAVE_REGNO\t\t108)\n (VSCR_REGNO\t\t\t109)\n (FRAME_POINTER_REGNUM\t110)\n+ (FIRST_DM_REGNO\t\t111)\n+ (LAST_DM_REGNO\t\t118)\n ])\n \n ;;\n", "prefixes": [] }