Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2225409/?format=api
{ "id": 2225409, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225409/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/aebXuv4vaHKa4wiy@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<aebXuv4vaHKa4wiy@cowardly-lion.the-meissners.org>", "date": "2026-04-21T01:49:46", "name": "GCC 17.0 PowerPC: PR 108958: Simplify mtvsrdd to zero extend GPR DImode to VSX TImode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6e405e9f247faf53c5b1e97be622ce006e028512", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/1.1/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/aebXuv4vaHKa4wiy@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 500705, "url": "http://patchwork.ozlabs.org/api/1.1/series/500705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500705", "date": "2026-04-21T01:49:46", "name": "GCC 17.0 PowerPC: PR 108958: Simplify mtvsrdd to zero extend GPR DImode to VSX TImode", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500705/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225409/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225409/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=qplCr7OJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=qplCr7OJ", "sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com", "sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=148.163.158.5" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g050J5Tgqz1yHB\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 11:50:23 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 1991D4BA2E3C\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 01:50:21 +0000 (GMT)", "from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n [148.163.158.5])\n by sourceware.org (Postfix) with ESMTPS id 8F7BD4BA2E3C\n for <gcc-patches@gcc.gnu.org>; Tue, 21 Apr 2026 01:49:53 +0000 (GMT)", "from pps.filterd (m0356516.ppops.net [127.0.0.1])\n by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63KJhKRT2038846; Tue, 21 Apr 2026 01:49:52 GMT", "from ppma22.wdc07v.mail.ibm.com\n (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92])\n by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4dm2h9hjku-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 21 Apr 2026 01:49:52 +0000 (GMT)", "from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1])\n by ppma22.wdc07v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id\n 63L1ZINQ005096;\n Tue, 21 Apr 2026 01:49:51 GMT", "from smtprelay02.wdc07v.mail.ibm.com ([172.16.1.69])\n by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4dmmnvq27k-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 21 Apr 2026 01:49:51 +0000 (GMT)", "from smtpav02.wdc07v.mail.ibm.com (smtpav02.wdc07v.mail.ibm.com\n [10.39.53.229])\n by smtprelay02.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 63L1nnpM32178760\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Tue, 21 Apr 2026 01:49:49 GMT", "from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 6DFA758058;\n Tue, 21 Apr 2026 01:49:49 +0000 (GMT)", "from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 55E775805B;\n Tue, 21 Apr 2026 01:49:48 +0000 (GMT)", "from cowardly-lion.the-meissners.org (unknown [9.61.149.99])\n by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTPS;\n Tue, 21 Apr 2026 01:49:48 +0000 (GMT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 1991D4BA2E3C", "OpenDKIM Filter v2.11.0 sourceware.org 8F7BD4BA2E3C" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 8F7BD4BA2E3C", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 8F7BD4BA2E3C", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1776736193; cv=none;\n b=F7C+WrHnaZBL6EJFrKk5Uz3QTrv0GwsPgSN8J86KDKqqUVuQ3NRlUZLaryVF4QXOUKCNAXTVHjbrQaNuBiF+u7Th/cNXZG/epTdgrfDOrvQ5mYTsVMcKo9OtZ5wDJdcve3yUT5dnaooUI1GmnUhdOIEfEjwwL105/4Xj97Hc7Vo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776736193; c=relaxed/simple;\n bh=ZXygbc0uArqodCAmBEGQ5mlxqNRNCVeHXl+6uZ+ZMcc=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=IA3GxkB10OwoRTH2JUSXw+K6dO7yonqX/ke4LlL5yeuAKq5AVyvlLJMENxVy/mMAOrtkKMs9mfxRJ1KHDlIwJZs2dYdD32z6iCjtIdFiAuf/sew7MJLb/A+oG+C0lQa/qkxS7QTQGLchVFyu1rEF+wW6w3FE+Q8IpIPzGsDqGsk=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=Y1CPJJsvgoNEd7H/0MgGtUQK5K9fti\n g0UBhFTRjJKIY=; b=qplCr7OJQPUqWoPFFMF7dEZZdeLPO9TgoZD1L8YMHjCEWH\n qIUOGsEa0+xEPMlNdKBTfD59hMpJD+E7ob76qs0hT4EF1OVoUTd4qdfwlsbz/zom\n hlUsW3DvGMpqkE1JTVdhxDoz8ZaM+KsIcZVoJv79xE7yzxces1/G3YZHZXWejAVV\n s1qcjq5wqndHAh37rWkjNypeZtksi2IjLaByXgIVKKBtkzMX4YvvREke64mXR/Xe\n dmjLsKJjRFEsHRcLbmni9SfFosSzxn8tJJdBqGZyZ9EaZhQ1yBF6qJiIM+6UtXtk\n j4QRqi2vSi0ZX3z94nps97Mj/2dMxBB/5RVxLhlQ==", "Date": "Mon, 20 Apr 2026 21:49:46 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17.0 PowerPC: PR 108958: Simplify mtvsrdd to zero extend GPR\n DImode to VSX TImode", "Message-ID": "<aebXuv4vaHKa4wiy@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<aebT1QQbPenBOFeH@cowardly-lion.the-meissners.org>\n <aebVA81k-W4V5Z3w@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<aebVA81k-W4V5Z3w@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Proofpoint-ORIG-GUID": "1WiEo2sbehbXNOMcU1vi5wSPSEUm7Tp-", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDAxNiBTYWx0ZWRfXxgcqvjhWZdID\n RDopupABF1koy8ozo4JZ87z2XFaChWNVMIaIXxg0g82p6Vx5MctlxfL7jBviJkRkN+LvKc13Pg0\n OaUAZlWlu6rx8h5zUbzH93lSVTACtkVXYFQbrGCKPs84h+btn8gwGnL8uVx/uMk0wVxheF4ilN+\n WGsnG5mw0eWDPpqLoFmdWYOzD6vOxV9w8gxh15LQ69VxSaVI+9XIEwoyzR+oDYCs3ml+Kb2icFf\n wW69WMCzRhs6hTJ06OQd/226/lL2FMG9p2j8RqUWOlvCZEhcEUH+vFjfCC+g3HgCkha02+VrVX3\n 7xH7iHmqnOOCNHtSMew/vg7/8+QbU53wIQPuOwUbp1WCxV1gKBpCYuxgSB3HnMLnLWw3hQ70Nea\n zFEd9bz0ZT48VOHUt3wG28/yBBN4qT5X0u29LsNqavHgsOMD0dvRbutNP7eVBd8Tl+BUtus3AnP\n bRpRdulOAaCVN7tyA5Q==", "X-Authority-Analysis": "v=2.4 cv=XLYAjwhE c=1 sm=1 tr=0 ts=69e6d7c0 cx=c_pps\n a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=Y2IxJ9c9Rs8Kov3niI8_:22 a=VnNF1IyMAAAA:8\n a=s0B0mPq8cDy_DPxwTYAA:9 a=CjuIK1q_8ugA:10", "X-Proofpoint-GUID": "1WiEo2sbehbXNOMcU1vi5wSPSEUm7Tp-", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 bulkscore=0 impostorscore=0 spamscore=0 adultscore=0\n priorityscore=1501 phishscore=0 lowpriorityscore=0 malwarescore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000\n definitions=main-2604210016", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Before this patch GCC would zero extend a DImode GPR value to TImode by first\nzero extending the DImode value into a GPR TImode register pair, and then do a\nMTVSRDD to move this value to a VSX register.\n\nFor example, consider the following code:\n\n\t#ifndef TYPE\n\t#define TYPE unsigned long long\n\t#endif\n\n\tvoid\n\tgpr_to_vsx (TYPE x, __uint128_t *p)\n\t{\n\t __uint128_t y = x;\n\t __asm__ (\" # %x0\" : \"+wa\" (y));\n\t *p = y;\n\t}\n\nCurrently GCC generates:\n\n\tgpr_to_vsx:\n\t\tmr 10,3\n\t\tli 11,0\n\t\tmtvsrdd 0,11,10\n\t#APP\n\t\t # 0\n\t#NO_APP\n\t\tstxv 0,0(4)\n\t\tblr\n\nI.e. the mr and li instructions create the zero extended TImode value\nin a GPR, and then the mtvsrdd instruction moves both registers into a\nsingle vector register.\n\nInstead, GCC should generate the following code. Since the mtvsrdd\ninstruction will clear the upper 64 bits if the 2nd argument is 0\n(non-zero values are a GPR to put in the upper 64 bits):\n\n\tgpr_to_vsx:\n\t\tmtvsrdd 0,0,3\n\t#APP\n\t\t # 0\n\t#NO_APP\n\t\tstxv 0,0(4)\n\t\tblr\n\nOriginally, I posted a patch that added the zero_extendsiti2 insn. I\ngot some pushback about using reload_completed in the split portion of\nthe define_insn_and_split. However, this is a case where you\nabsolutely have to use the reload_completed test, because if you split\nthe code before register allocation to handle the normal, the split\ninsns will not be compiled to generate the appropriate mtvsrdd without\ncreating the TImode value in the GPR register. I can imagine there\nmight be concern about favoring generating code using the vector\nregisters instead of using the GPR registers if the code does not\nrequire the TImode value to be in a vector register.\n\nI completely rewrote the patch. This patch creates a peephole2 to\ncatch this case, and it eliminates creating the TImode variable.\nInstead it just does the MTVSRDD instruction directly. That way it\nwill not influence register allocation, and the code will only be\ngenerated in the specific case where we need the TImode value in a\nvector register.\n\nI have built GCC with the patches in this patch set applied on both\nlittle and big endian PowerPC systems and there were no regressions.\nCan I apply this patch to GCC 17?\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\ngcc/\n\n\tPR target/108958\n\t* config/rs6000/rs6000.md (UNSPEC_ZERO_EXTEND): New unspec.\n\t(zero_extendsiti2 peephole2): Add a peephole2 to simplify zero\n\textend between DImode value in a GPR to a TImode target in a\n\tvector register.\n\t(zero_extendsiti2_vsx): New insn.\n\ngcc/testsuite/\n\n\tPR target/108958\n\t* gcc.target/powerpc/pr108958.c: New test.\n---\n gcc/config/rs6000/rs6000.md | 26 ++++++++++++\n gcc/testsuite/gcc.target/powerpc/pr108958.c | 47 +++++++++++++++++++++\n 2 files changed, 73 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108958.c", "diff": "diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\nindex ed724ff8058..dbdc2eef2df 100644\n--- a/gcc/config/rs6000/rs6000.md\n+++ b/gcc/config/rs6000/rs6000.md\n@@ -173,6 +173,7 @@ (define_c_enum \"unspec\"\n UNSPEC_XXSPLTIW_CONST\n UNSPEC_FMAX\n UNSPEC_FMIN\n+ UNSPEC_ZERO_EXTEND\n ])\n \n ;;\n@@ -969,6 +970,31 @@ (define_insn_and_split \"*zero_extendhi<mode>2_dot2\"\n (set_attr \"dot\" \"yes\")\n (set_attr \"length\" \"4,8\")])\n \n+;; Optimize zero_extendsiti2 from a GPR to a GPR and then moving the GPR to a\n+;; VSX register\n+(define_peephole2\n+ [(set (match_operand:DI 0 \"int_reg_operand\")\n+\t(match_operand:DI 1 \"int_reg_operand\"))\n+ (set (match_operand:DI 2 \"int_reg_operand\")\n+\t(const_int 0))\n+ (set (match_operand:TI 3 \"vsx_register_operand\")\n+\t(match_operand:TI 4 \"int_reg_operand\"))]\n+ \"TARGET_DIRECT_MOVE_64BIT\n+ && (reg_or_subregno (operands[0])\n+ == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)\n+ && (reg_or_subregno (operands[2])\n+ == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)\n+ && peep2_reg_dead_p (3, operands[4])\"\n+ [(set (match_dup 3)\n+\t(unspec:TI [(match_dup 1)] UNSPEC_ZERO_EXTEND))])\n+\n+(define_insn \"*zero_extendsiti2_vsx\"\n+ [(set (match_operand:TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:TI [(match_operand:DI 1 \"int_reg_operand\" \"r\")]\n+\t\t UNSPEC_ZERO_EXTEND))]\n+ \"TARGET_DIRECT_MOVE_64BIT\"\n+ \"mtvsrdd %x0,0,%1\"\n+ [(set_attr \"type\" \"mtvsr\")])\n \n ;; On power10, optimize zero extending a QI/HI/SI/DImode value from memory that\n ;; is going to a vector register target by generating a LXVR{B,H,W,D}X\ndiff --git a/gcc/testsuite/gcc.target/powerpc/pr108958.c b/gcc/testsuite/gcc.target/powerpc/pr108958.c\nnew file mode 100644\nindex 00000000000..21b3f276691\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/pr108958.c\n@@ -0,0 +1,47 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target int128 } */\n+/* { dg-require-effective-target lp64 } */\n+/* { dg-options \"-mdejagnu-cpu=power9 -O2\" } */\n+\n+#ifndef TYPE\n+#define TYPE unsigned long long\n+#endif\n+\n+/* PR target/108958, when zero extending a DImode to a TImode, and the TImode variable is in a VSX register, generate:\n+\n+\tmtvsrdd vreg,0,gpr\n+\n+ instead of:\n+\n+\tmr tmp,gpr\n+\tli tmp+1,0\n+\tmtvsrdd vreg,tmp+1,tmp. */\n+\n+void\n+gpr_to_vsx (TYPE x, __uint128_t *p)\n+{\n+ /* mtvsrdd 0,0,3\n+ stvx 0,0(4) */\n+\n+ __uint128_t y = x;\n+ __asm__ (\" # %x0\" : \"+wa\" (y));\n+ *p = y;\n+}\n+\n+void\n+gpr_to_gpr (TYPE x, __uint128_t *p)\n+{\n+ /* mr 2,3\n+ li 3,0\n+ std 2,0(4)\n+ std 3,8(4) */\n+\n+ __uint128_t y = x;\n+ __asm__ (\" # %0\" : \"+r\" (y));\n+ *p = y;\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mli\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mmtvsrdd .*,0,.*\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mstd\\M} 2 } } */\n+/* { dg-final { scan-assembler-times {\\mstxv\\M} 1 } } */\n", "prefixes": [] }