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{ "id": 2225408, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225408/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/aebXRgQKgTGhazF3@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<aebXRgQKgTGhazF3@cowardly-lion.the-meissners.org>", "date": "2026-04-21T01:47:50", "name": "GCC 17.0 PowerPC: PR 120528: Simplify zero extend from memory to VSX register on power10/power11", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "21d14d5ce0f525c514c8e393cf2579dc515ab2a4", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/1.1/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/aebXRgQKgTGhazF3@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 500704, "url": "http://patchwork.ozlabs.org/api/1.1/series/500704/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500704", "date": "2026-04-21T01:47:50", "name": "GCC 17.0 PowerPC: PR 120528: Simplify zero extend from memory to VSX register on power10/power11", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500704/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225408/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225408/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=dDib+2fN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1776736076; cv=none;\n b=j4hAfHDWrD2Ehu6i3k02HAugMgZG1tAQXlh0CDFighVvBNRgS9Kz711MlpVLwpwKTuK7Oynq4d2kufM3ntWqJwRn7MWl92TfDztyBC5HowIWQsQOHuizncNGGW2Jnbz8k8J2KbqG/DvjKPW/MD7A+Z3BEAvTyCyNq17G/AkFLGQ=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776736076; c=relaxed/simple;\n bh=0W2LVYqIjFRzub13dYaCo1hp8kXIXe2DdnNjU7uS4tU=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=UNggSL65Iactu6/bn6WBj2YdtAHkKA8Dx4nALRnCygc8DiWNemP9qwHtFgrm/QKYbFrKbjL3/GnbUPK5Hwk6SWbfX9sPd0GkqMvBnnryErnCFieTYO+iQyNfJCGqq8ERYTUDmmkWwoE4FcOEA+XB1DXXjtBddxZ56YjbEBZ0l7o=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=IftvmeWJHQ+2JWUuP1HnmNfchnJ/hi\n M1oDcyaKDuujA=; b=dDib+2fNPxneMCPDOnTj0BEx2hwlHEYHRJ+LUYSpWMDU7C\n 3XUvF+XocF4nK1hYyxQ+t2TkJ0GGOolG+jfBSaJufa8hVfsKNn1/+aJf8C9x4G7m\n cOYBXqarqC24W5UG3GQGzl/efhmz9wjQUMpHfqpb0z6uaRw3rxxLazQUz8+N2YR0\n nYH2DTc53R66rjiX2YVmMvtG09vofpr/czlgmcKBYQ8+B+gvM19/4zbAn0oMpbdr\n wzWm/AJGfc5d/dfzmTGT7nOBPrRyC68rlAo56ixd3NjBlXgMfq304s88ZiZAI4Tb\n saFCJGEq7Y/XPiBVq86H/MUmA7XeMpjHuvl0ZmeA==", "Date": "Mon, 20 Apr 2026 21:47:50 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17.0 PowerPC: PR 120528: Simplify zero extend from memory to VSX\n register on power10/power11", "Message-ID": "<aebXRgQKgTGhazF3@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<aebT1QQbPenBOFeH@cowardly-lion.the-meissners.org>\n <aebVA81k-W4V5Z3w@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<aebVA81k-W4V5Z3w@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Proofpoint-ORIG-GUID": "1TQzh1Y1917h7LdqjnyB7zZGCT_ThODy", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDAxNiBTYWx0ZWRfX/thlrzQezWL/\n sfdehTjwLeiwdCnsDUtXW3r7K7UvS7czM3Q357/0qsAooqj5XXSuDTmowZcgKMr4xpFPSwJLRiK\n F68q7t52IgFOfuNFOXrEWvoW/KkW8qfYQnMxhRsULEqvg774t5Gp/y2lowg0p8vrAtTsEcQQaVK\n MS1HOj1cRzxXOgNuj7+4a0rqlP4QfcKw46tFnwDw+A1nex+2fUA9rTFmnSiDwZXjq0CQrg+U9sR\n cIBvXE9N+jSDyvZw3oklweH7yXM3w+6rVhkufapMJgch3JaVQyhlQjgEJYUP4HEuFhg6jway9ZW\n Ikm93MyH+1nuNv+okQMz4lYDexuLOn/+M2nrMDUawZIrRlmniuSEEC5bHDANwfav75uToWhO7XS\n tXBTTrKxv2Co4WeXRRi2O+efnF5YXIMpBdQxSFfEdLYoYCQSJzKb1tF9+wIx/6UNf9I4bl5zjMY\n 0X4e5cRRV4UHFaxYlKg==", "X-Authority-Analysis": "v=2.4 cv=PtujqQM3 c=1 sm=1 tr=0 ts=69e6d74b cx=c_pps\n a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=VnNF1IyMAAAA:8\n a=twwvKAmvcN4dd9Nw6wwA:9 a=CjuIK1q_8ugA:10", "X-Proofpoint-GUID": "1TQzh1Y1917h7LdqjnyB7zZGCT_ThODy", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0 clxscore=1015 spamscore=0 impostorscore=0\n priorityscore=1501 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210016", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Previously GCC would zero extend a DImode value in memory to a TImode\ntarget in a vector register by firt zero extending the DImode value\ninto a GPR TImode register pair, and then do a MTVSRDD to move this\nvalue to a VSX register.\n\nFor example, consider the following code:\n\n\t#ifndef TYPE\n\t#define TYPE unsigned long long\n\t#endif\n\n\tvoid\n\tmem_to_vsx (TYPE *p, __uint128_t *q)\n\t{\n\t /* lxvrdx 0,0,3\n\t stxv 0,0(4) */\n\n\t __uint128_t x = *p;\n\t __asm__ (\" # %x0\" : \"+wa\" (x));\n\t *q = x;\n\t}\n\nIt currently generates the following code on power10:\n\n\tmem_to_vsx:\n\t\tld 10,0(3)\n\t\tli 11,0\n\t\tmtvsrdd 0,11,10\n\t#APP\n\t\t # 0\n\t#NO_APP\n\t\tstxv 0,0(4)\n\t\tblr\n\nInstead it could generate:\n\n\tmem_to_vsx:\n\t\tlxvrdx 0,0,3\n\t#APP\n\t\t # 0\n\t#NO_APP\n\t\tstxv 0,0(4)\n\t\tblr\n\nThe lxvr{b,h,w,d}x instructions were added in power10, and they load up\na vector register with a byte, half-word, word, or double-word value in\nthe right most bits, and fill the remaining bits to 0. I noticed this\ncode when working on PR target/108958 (which I just posted the patch).\n\nThis patch creates a peephole2 to catch this case, and it eliminates\ncreating the TImode variable. Instead it just does the LXVR{B,H,W,D}x\ninstruction directly.\n\nI have built GCC with the patches in this patch set applied on both\nlittle and big endian PowerPC systems and there were no regressions.\nCan I apply this patch to GCC 17?\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\ngcc/\n\n\tPR target/120528\n\t* config/rs6000/rs6000.md (zero_extend??ti2 peephole2): Add a\n\tpeephole2 to simplify zero extending a QI/HI/SI/DImode value in\n\tmemory to a TImode target in a vector register to use the\n\tLXVR{B,H,W,D}X instructins.\n\ngcc/testsuite/\n\n\tPR target/120528\n\t* gcc.target/powerpc/pr120528.c: New test.\n---\n gcc/config/rs6000/rs6000.md | 69 ++++++++++++++++\n gcc/testsuite/gcc.target/powerpc/pr120528.c | 91 +++++++++++++++++++++\n 2 files changed, 160 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/pr120528.c", "diff": "diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\nindex 3089551552c..ed724ff8058 100644\n--- a/gcc/config/rs6000/rs6000.md\n+++ b/gcc/config/rs6000/rs6000.md\n@@ -970,6 +970,75 @@ (define_insn_and_split \"*zero_extendhi<mode>2_dot2\"\n (set_attr \"length\" \"4,8\")])\n \n \n+;; On power10, optimize zero extending a QI/HI/SI/DImode value from memory that\n+;; is going to a vector register target by generating a LXVR{B,H,W,D}X\n+;; instruction without creating the TImode value in a GPR and using MTVSRDD to\n+;; move it to the vector register.\n+(define_peephole2\n+ [(set (match_operand:DI 0 \"int_reg_operand\")\n+\t(match_operand:DI 1 \"memory_operand\"))\n+ (set (match_operand:DI 2 \"base_reg_operand\")\n+\t(const_int 0))\n+ (set (match_operand:TI 3 \"vsx_register_operand\")\n+\t(match_operand:TI 4 \"int_reg_operand\"))]\n+ \"TARGET_POWER10 && TARGET_POWERPC64\n+ && (reg_or_subregno (operands[0])\n+ == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)\n+ && (reg_or_subregno (operands[2])\n+ == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)\n+ && peep2_reg_dead_p (3, operands[4])\n+ && (REG_P (XEXP (operands[1], 0))\n+ || SUBREG_P (XEXP (operands[1], 0))\n+ || GET_CODE (XEXP (operands[1], 0)) == PLUS)\"\n+ [(set (match_dup 3)\n+\t(zero_extend:TI (match_dup 5)))]\n+{\n+ rtx mem = operands[1];\n+ rtx addr = XEXP (mem, 0);\n+\n+ if (indexed_or_indirect_address (addr, DImode))\n+ operands[5] = mem;\n+ else\n+ {\n+ rtx op2 = operands[2];\n+ emit_insn (gen_rtx_SET (op2, addr));\n+ operands[5] = change_address (mem, DImode, op2);\n+ }\n+})\n+\n+(define_peephole2\n+ [(set (match_operand:DI 0 \"int_reg_operand\")\n+\t(zero_extend:DI\n+\t (match_operand:QHSI 1 \"memory_operand\")))\n+ (set (match_operand:DI 2 \"base_reg_operand\")\n+\t(const_int 0))\n+ (set (match_operand:TI 3 \"vsx_register_operand\")\n+\t(match_operand:TI 4 \"int_reg_operand\"))]\n+ \"TARGET_POWER10 && TARGET_POWERPC64\n+ && (reg_or_subregno (operands[0])\n+ == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)\n+ && (reg_or_subregno (operands[2])\n+ == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)\n+ && peep2_reg_dead_p (3, operands[4])\n+ && (REG_P (XEXP (operands[1], 0))\n+ || SUBREG_P (XEXP (operands[1], 0))\n+ || GET_CODE (XEXP (operands[1], 0)) == PLUS)\"\n+ [(set (match_dup 3)\n+\t(zero_extend:TI (match_dup 5)))]\n+{\n+ rtx mem = operands[1];\n+ rtx addr = XEXP (mem, 0);\n+\n+ if (indexed_or_indirect_address (addr, DImode))\n+ operands[5] = mem;\n+ else\n+ {\n+ rtx op2 = operands[2];\n+ emit_insn (gen_rtx_SET (op2, addr));\n+ operands[5] = change_address (mem, DImode, op2);\n+ }\n+})\n+\n (define_insn \"zero_extendsi<mode>2\"\n [(set (match_operand:EXTSI 0 \"gpc_reg_operand\" \"=r,r,d,wa,wa,r,wa\")\n \t(zero_extend:EXTSI (match_operand:SI 1 \"reg_or_mem_operand\" \"m,r,?Z,?Z,r,wa,wa\")))]\ndiff --git a/gcc/testsuite/gcc.target/powerpc/pr120528.c b/gcc/testsuite/gcc.target/powerpc/pr120528.c\nnew file mode 100644\nindex 00000000000..476725eaa4f\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/pr120528.c\n@@ -0,0 +1,91 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target int128 } */\n+/* { dg-require-effective-target lp64 } */\n+/* { dg-require-effective-target power10_ok } */\n+/* { dg-options \"-mdejagnu-cpu=power10 -O2\" } */\n+\n+#include <stddef.h>\n+\n+#ifndef TYPE\n+#define TYPE unsigned long long\n+#endif\n+\n+void\n+mem_to_vsx (TYPE *p, __uint128_t *q)\n+{\n+ /* lxvrdx 0,0,3\n+ stxv 0,0(4) */\n+\n+ __uint128_t x = *p;\n+ __asm__ (\" # %x0\" : \"+wa\" (x));\n+ *q = x;\n+}\n+\n+void\n+memx_to_vsx (TYPE *p, size_t n, __uint128_t *q)\n+{\n+ /* sldi 4,4,3\n+ lxvrdx 0,3,4\n+ stxv 0,0(4) */\n+\n+ __uint128_t x = p[n];\n+ __asm__ (\" # %x0\" : \"+wa\" (x));\n+ *q = x;\n+}\n+\n+void\n+mem3_to_vsx (TYPE *p, __uint128_t *q)\n+{\n+ /* addi 2,3,24\n+ lxvrdx 0,0,2\n+ stxv 0,0(4) */\n+\n+ __uint128_t x = p[3];\n+ __asm__ (\" # %x0\" : \"+wa\" (x));\n+ *q = x;\n+}\n+\n+void\n+mem_to_gpr (TYPE *p, __uint128_t *q)\n+{\n+ /* ld 2,0(3)\n+ li 3,0\n+ std 2,0(4)\n+ std 3,8(8) */\n+\n+ __uint128_t x = *p;\n+ __asm__ (\" # %0\" : \"+r\" (x));\n+ *q = x;\n+}\n+\n+void\n+memx_to_gpr (TYPE *p, size_t n, __uint128_t *q)\n+{\n+ /* sldi 4,4,3\n+ ldx 2,3,4\n+ li 3,0\n+ std 2,0(4)\n+ std 3,8(8) */\n+\n+ __uint128_t x = p[n];\n+ __asm__ (\" # %0\" : \"+r\" (x));\n+ *q = x;\n+}\n+\n+void\n+mem3_to_gpr (TYPE *p, __uint128_t *q)\n+{\n+ /* ld 2,24(3)\n+ li 3,0\n+ std 2,0(4)\n+ std 3,8(8) */\n+\n+ __uint128_t x = p[3];\n+ __asm__ (\" # %0\" : \"+r\" (x));\n+ *q = x;\n+}\n+\n+/* { dg-final { scan-assembler-times {\\maddi\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mli\\M} 3 } } */\n+/* { dg-final { scan-assembler-times {\\mlxvrdx\\M} 3 } } */\n+/* { dg-final { scan-assembler-times {\\mstxv\\M} 3 } } */\n", "prefixes": [] }