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{ "id": 2225406, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225406/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/aebVvgkL8Jfmau3O@cowardly-lion.the-meissners.org/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<aebVvgkL8Jfmau3O@cowardly-lion.the-meissners.org>", "date": "2026-04-21T01:41:18", "name": "GCC 17.0 PowerPC: PR 117487: Add power9 and power10 float to logical optimizations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "79981b7da95d5636c731d6c2e9f4ccb827bc2957", "submitter": { "id": 73991, "url": "http://patchwork.ozlabs.org/api/1.1/people/73991/?format=api", "name": "Michael Meissner", "email": "meissner@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/aebVvgkL8Jfmau3O@cowardly-lion.the-meissners.org/mbox/", "series": [ { "id": 500702, "url": "http://patchwork.ozlabs.org/api/1.1/series/500702/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500702", "date": "2026-04-21T01:41:18", "name": "GCC 17.0 PowerPC: PR 117487: Add power9 and power10 float to logical optimizations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500702/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225406/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225406/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=MmRRsJq5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; d=sourceware.org; s=key; t=1776735686; cv=none;\n b=hitmEe1ZXFyEzNcprGsSMlwYJQWkkxVoiUvokzpUMV5Ka7dkmAgNmsCkaShaRc7nhs0IADAtQRoJMwWc69WjyNYqVaPMiQKCp9cJuTuDZF1V0QPJ0tkOMV8+8PQ1RpRj544G7E7c6ogbfLZDzPY3IyqDmJr6e1pIJzHnypqJmWE=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1776735686; c=relaxed/simple;\n bh=qFXDtQMqhWcSldHs1vFePFWd4ZoQ29b35HxZpLWmu14=;\n h=DKIM-Signature:Date:From:To:Subject:Message-ID:MIME-Version;\n b=DQAtxPSHr95aILXR1DNmheScxXkxwI8kc1W0OFUDtieP/cz1nwjbMvojmE50RWoLOXe+taVv7/QjY7Sx7aepHjW2dC6gYlj00DVgvSBFY6EsHnyvZrnUeBCMB2C+4qnjYeRKHfErzNYNTgT+7f2Lgmg/ca4pr4uwUWbvZ/sBS+s=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=\n content-type:date:from:in-reply-to:message-id:mime-version\n :references:subject:to; s=pp1; bh=Ka1XU+74Cu3nWv2KcBRNO7GR/nTHvA\n hlkPa+h7cDqx4=; b=MmRRsJq5uy71jbUIKCohYLk6cYdr5HmuJGHSrK3wgtjCIj\n 6tXSB69FMmgcg8FZsDQuBF6dbq3zmk7PlT1GHcOcGJRjt/GkretXZ8UN52Dqaf2V\n EEZqxNe+KEpV0p+oNBNYZen15AX0tTuIN+8yKcaoUmTXXNy4YG67p+ku78Efp5Il\n e5ETW9xDmuvORXtnlQ3MZ4wiIOMhidy1BK0SCDJd9ggsoEy/y8oBNDpxqM1UkrS8\n RCUF2qezApR58oEtgC75Do2BU+PjGpKJQ9vScncopiEU3FFYiva+Hy99iM4XWlSp\n FCTdKPn+m7UGCjFj7zG5VVsQWiYMgthtNPGkVbdg==", "Date": "Mon, 20 Apr 2026 21:41:18 -0400", "From": "Michael Meissner <meissner@linux.ibm.com>", "To": "Michael Meissner <meissner@linux.ibm.com>, gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "Subject": "GCC 17.0 PowerPC: PR 117487: Add power9 and power10 float to logical\n optimizations", "Message-ID": "<aebVvgkL8Jfmau3O@cowardly-lion.the-meissners.org>", "Mail-Followup-To": "Michael Meissner <meissner@linux.ibm.com>,\n gcc-patches@gcc.gnu.org,\n Segher Boessenkool <segher@kernel.crashing.org>,\n jeevitha <jeevitha@linux.ibm.com>,\n Surya Kumari Jangala <jskumari@linux.ibm.com>,\n Kishan Parmar <kishan@linux.ibm.com>,\n Avinash Jayakar <avinashd@linux.ibm.com>,\n Ayappan Perumal <ayappap2@in.ibm.com>,\n Juergen Christ <jchrist@linux.ibm.com>", "References": "<aebT1QQbPenBOFeH@cowardly-lion.the-meissners.org>\n <aebVA81k-W4V5Z3w@cowardly-lion.the-meissners.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<aebVA81k-W4V5Z3w@cowardly-lion.the-meissners.org>", "X-TM-AS-GCONF": "00", "X-Proofpoint-ORIG-GUID": "rqrzZ8lfoJJs6YB41paAjBMQCBUcDUqE", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIxMDAxMSBTYWx0ZWRfX78pKBL5eF4lK\n lVgYq7BxUHIR3hLg4luwRmxeoJbrUKx+YGwbFJIrwnS97hiK39UHQz/oUeq2sj6xzNE0bcHxIZK\n qmHUwYND//lsY1Ci9PrCAo7kkzW2a6ZGpP9I2AaUyHUmVUF7P8qMv3XH2CCAg9rXV+f21ZhwIO0\n QUE28lIi5Y5jYQNwzF3LCWsYIIOeNqFCs+CW6c955FkLgRi4j+6NyFizLvMltZosJoN4iq8TBAc\n cJW+iPIVluceUZaz/6YdktwG/toIB7BRmAjv67qgsPDGPTQzUovAmuGC2fjlZytCZDk3/d20x68\n vFHzazXK04FDIjIrfOUbk7G0Cx5sMximkOFQ5XSc7GWpbKSjhdlW1EciSsKcm8Y8BK4d+Z5HJnK\n 5Ao1d2TDgZ3cgA+OxODnl05m0H3WkQOOf48sMRZtaDhL0uWlzBpAdLsjSqQnLmTtG0kG92x/aZm\n KwYz9Gf2jK/MTcQob4A==", "X-Proofpoint-GUID": "rqrzZ8lfoJJs6YB41paAjBMQCBUcDUqE", "X-Authority-Analysis": "v=2.4 cv=B7iJFutM c=1 sm=1 tr=0 ts=69e6d5c5 cx=c_pps\n a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8\n a=CSi3jQvmZEiN3mF49G0A:9 a=CjuIK1q_8ugA:10", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_05,2026-04-20_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 priorityscore=1501 spamscore=0 impostorscore=0 adultscore=0\n bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210011", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "I was answering an email from a co-worker (some time ago) and I pointed\nhim to work I had done for the Power8 era that optimizes the 32-bit\nfloat math library in Glibc. In doing so, I discovered with the Power9\nand later computers, this optimization is no longer taking place.\n\nThe glibc 32-bit floating point math functions have code that looks like:\n\n\tunion u {\n\t float f;\n\t uint32_t u32;\n\t};\n\n\tfloat\n\tmath_foo (float x, unsigned int mask)\n\t{\n\t union u arg;\n\t float x2;\n\n\t arg.f = x;\n\t arg.u32 &= mask;\n\n\t x2 = arg.f;\n\t /* ... */\n\t}\n\nOn power8 with the optimization it generates:\n\n xscvdpspn 0,1\n sldi 9,4,32\n mtvsrd 32,9\n xxland 1,0,32\n xscvspdpn 1,1\n\nI.e., it converts the SFmode to the memory format (instead of the DFmode that is\nused within the register), converts the mask so that it is in the vector\nregister in the upper 32-bits, and does a XXLAND (i.e. there is only one direct\nmove from GPR to vector register). Then after doing this, it converts the\nupper 32-bits back to DFmode.\n\nIf the XSCVSPDN instruction took the value in the normal 32-bit scalar in a\nvector register, we wouldn't have needed the SLDI of the mask.\n\nOn power9/power10/power11 it currently generates:\n\n xscvdpspn 0,1\n mfvsrwz 2,0\n and 2,2,4\n mtvsrws 1,2\n xscvspdpn 1,1\n blr\n\nI.e convert to SFmode representation, move the value to a GPR, do an AND\noperation, move the 32-bit value with a splat, and then convert it back to\nDFmode format.\n\nWith this patch, it now generates:\n\n xscvdpspn 0,1\n mtvsrwz 32,2\n xxland 32,0,32\n xxspltw 1,32,1\n xscvspdpn 1,1\n blr\n\nI.e. convert to SFmode representation, move the mask to the vector register, do\nthe operation using XXLAND. Splat the value to get the value in the correct\nlocation, and then convert back to DFmode.\n\nI have built GCC with the patches in this patch set applied on both little and\nbig endian PowerPC systems and there were no regressions. Can I apply\nthis patch to the trunk when GCC 17 opens up?\n\n2026-04-20 Michael Meissner <meissner@linux.ibm.com>\n\ngcc/\n\n\tPR target/117487\n\t* config/rs6000/vsx.md (SFmode logical peephoole): Update comments in\n\tthe original code that supports power8.\n\t(SFBOOL2_*): New constants.\n\t(power9/power10 define_peephol2): Add a new define_peephole2 to optimize\n\tfloat and logical operations on power9/power10/power11 similar to the\n\toptimiztion that is done on power8.\n\ngcc/testsuite/\n\n\tPR target/117487\n\t* gcc.target/powerpc/pr117487.c: New test.\n---\n gcc/config/rs6000/vsx.md | 142 +++++++++++++++++++-\n gcc/testsuite/gcc.target/powerpc/pr117487.c | 67 +++++++++\n 2 files changed, 204 insertions(+), 5 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/pr117487.c", "diff": "diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex cfad9b8c6d5..504f86e0ba8 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -6265,7 +6265,7 @@ (define_constants\n (SFBOOL_MFVSR_A\t\t 3)\t\t;; move to gpr src\n (SFBOOL_BOOL_D\t\t 4)\t\t;; and/ior/xor dest\n (SFBOOL_BOOL_A1\t\t 5)\t\t;; and/ior/xor arg1\n- (SFBOOL_BOOL_A2\t\t 6)\t\t;; and/ior/xor arg1\n+ (SFBOOL_BOOL_A2\t\t 6)\t\t;; and/ior/xor arg2\n (SFBOOL_SHL_D\t\t 7)\t\t;; shift left dest\n (SFBOOL_SHL_A\t\t 8)\t\t;; shift left arg\n (SFBOOL_MTVSR_D\t\t 9)\t\t;; move to vecter dest\n@@ -6305,18 +6305,18 @@ (define_constants\n ;; GPR, and instead move the integer mask value to the vector register after a\n ;; shift and do the VSX logical operation.\n \n-;; The insns for dealing with SFmode in GPR registers looks like:\n+;; The insns for dealing with SFmode in GPR registers looks like on power8:\n ;; (set (reg:V4SF reg2) (unspec:V4SF [(reg:SF reg1)] UNSPEC_VSX_CVDPSPN))\n ;;\n-;; (set (reg:DI reg3) (unspec:DI [(reg:V4SF reg2)] UNSPEC_P8V_RELOAD_FROM_VSX))\n+;; (set (reg:DI reg3) (zero_extend:DI (reg:SI reg2)))\n ;;\n-;; (set (reg:DI reg4) (and:DI (reg:DI reg3) (reg:DI reg3)))\n+;; (set (reg:DI reg4) (and:SI (reg:SI reg3) (reg:SI mask)))\n ;;\n ;; (set (reg:DI reg5) (ashift:DI (reg:DI reg4) (const_int 32)))\n ;;\n ;; (set (reg:SF reg6) (unspec:SF [(reg:DI reg5)] UNSPEC_P8V_MTVSRD))\n ;;\n-;; (set (reg:SF reg6) (unspec:SF [(reg:SF reg6)] UNSPEC_VSX_CVSPDPN))\n+;; (set (reg:SF reg7) (unspec:SF [(reg:SF reg6)] UNSPEC_VSX_CVSPDPN))\n \n (define_peephole2\n [(match_scratch:DI SFBOOL_TMP_GPR \"r\")\n@@ -6397,6 +6397,138 @@ (define_peephole2\n operands[SFBOOL_MTVSR_D_V4SF] = gen_rtx_REG (V4SFmode, regno_mtvsr_d);\n })\n \n+;; Constants for SFbool optimization on power9/power10\n+(define_constants\n+ [(SFBOOL2_TMP_VSX_V4SI\t 0)\t\t;; vector temporary (V4SI)\n+ (SFBOOL2_TMP_GPR_SI\t\t 1)\t\t;; GPR temporary (SI)\n+ (SFBOOL2_MFVSR_D\t\t 2)\t\t;; move to gpr dest (DI)\n+ (SFBOOL2_MFVSR_A\t\t 3)\t\t;; move to gpr src (SI)\n+ (SFBOOL2_BOOL_D\t\t 4)\t\t;; and/ior/xor dest (SI)\n+ (SFBOOL2_BOOL_A1\t\t 5)\t\t;; and/ior/xor arg1 (SI)\n+ (SFBOOL2_BOOL_A2\t\t 6)\t\t;; and/ior/xor arg2 (SI)\n+ (SFBOOL2_SPLAT_D\t\t 7)\t\t;; splat dest (V4SI)\n+ (SFBOOL2_MTVSR_D\t\t 8)\t\t;; move/splat to VSX dest.\n+ (SFBOOL2_MTVSR_A\t\t 9)\t\t;; move/splat to VSX arg.\n+ (SFBOOL2_MFVSR_A_V4SI\t10)\t\t;; MFVSR_A as V4SI\n+ (SFBOOL2_MTVSR_D_V4SI\t11)\t\t;; MTVSR_D as V4SI\n+ (SFBOOL2_XXSPLTW\t\t12)])\t\t;; 1 or 3 for XXSPLTW\n+\n+;; On power9/power10, the code is different because we have a splat 32-bit\n+;; operation that does a direct move to the FPR/vector registers (MTVSRWS).\n+;;\n+;; The insns for dealing with SFmode in GPR registers looks like on\n+;; power9/power10:\n+;;\n+;; (set (reg:V4SF reg2) (unspec:V4SF [(reg:SF reg1)] UNSPEC_VSX_CVDPSPN))\n+;;\n+;; (set (reg:DI reg3) (zero_extend:DI (reg:SI reg2)))\n+;;\n+;; (set (reg:SI reg4) (and:SI (reg:SI reg3) (reg:SI mask)))\n+;;\n+;; (set (reg:V4SI reg5) (vec_duplicate:V4SI (reg:SI reg4)))\n+;;\n+;; (set (reg:SF reg6) (unspec:SF [(reg:SF reg5)] UNSPEC_VSX_CVSPDPN))\n+\n+;; The VSX temporary needs to be an Altivec register in case we are trying to\n+;; do and/ior/xor of -16..15 and we want to use VSPLTISW to load the constant.\n+;;\n+;; The GPR temporary is only used if we are trying to do a logical operation\n+;; with a constant outside of the -16..15 range on a power9. Otherwise, we can\n+;; load the constant directly into the VSX temporary register.\n+\n+(define_peephole2\n+ [(match_scratch:V4SI SFBOOL2_TMP_VSX_V4SI \"v\")\n+ (match_scratch:SI SFBOOL2_TMP_GPR_SI \"r\")\n+\n+ ;; Zero_extend and direct move\n+ (set (match_operand:DI SFBOOL2_MFVSR_D \"int_reg_operand\")\n+\t(zero_extend:DI\n+\t (match_operand:SI SFBOOL2_MFVSR_A \"vsx_register_operand\")))\n+\n+ ;; AND/IOR/XOR operation on int\n+ (set (match_operand:SI SFBOOL2_BOOL_D \"int_reg_operand\")\n+\t(and_ior_xor:SI\n+\t (match_operand:SI SFBOOL2_BOOL_A1 \"int_reg_operand\")\n+\t (match_operand:SI SFBOOL2_BOOL_A2 \"reg_or_cint_operand\")))\n+\n+ ;; Splat sfbool result to vector register\n+ (set (match_operand:V4SI SFBOOL2_SPLAT_D \"vsx_register_operand\")\n+\t(vec_duplicate:V4SI\n+\t (match_dup SFBOOL2_BOOL_D)))]\n+\n+ \"TARGET_POWERPC64 && TARGET_P9_VECTOR\n+ && REG_P (operands[SFBOOL2_MFVSR_D])\n+ && REG_P (operands[SFBOOL2_BOOL_A1])\n+ && (REGNO (operands[SFBOOL2_MFVSR_D]) == REGNO (operands[SFBOOL2_BOOL_A1])\n+ || (REG_P (operands[SFBOOL2_BOOL_A2])\n+ && (REGNO (operands[SFBOOL2_MFVSR_D])\n+ == REGNO (operands[SFBOOL2_BOOL_A2]))))\n+ && peep2_reg_dead_p (3, operands[SFBOOL2_MFVSR_D])\n+ && peep2_reg_dead_p (4, operands[SFBOOL2_BOOL_D])\"\n+\n+ ;; Either (set (reg:SI xxx) (reg:SI yyy))\tor\n+ ;; (set (reg:V4SI xxx) (const_vector (parallel [c, c, c, c])))\n+ [(set (match_dup SFBOOL2_MTVSR_D)\n+\t(match_dup SFBOOL2_MTVSR_A))\n+\n+ ;; And/ior/xor on vector registers\n+ (set (match_dup SFBOOL2_TMP_VSX_V4SI)\n+\t(and_ior_xor:V4SI\n+\t (match_dup SFBOOL2_MFVSR_A_V4SI)\n+\t (match_dup SFBOOL2_TMP_VSX_V4SI)))\n+\n+ ;; XXSPLTW t,r,r,1\n+ (set (match_dup SFBOOL2_SPLAT_D)\n+\t(vec_duplicate:V4SI\n+\t (vec_select:SI\n+\t (match_dup SFBOOL2_TMP_VSX_V4SI)\n+\t (parallel [(match_dup SFBOOL2_XXSPLTW)]))))]\n+{\n+ rtx mfvsr_d = operands[SFBOOL2_MFVSR_D];\n+ rtx bool_a1 = operands[SFBOOL2_BOOL_A1];\n+ rtx bool_a2 = operands[SFBOOL2_BOOL_A2];\n+ rtx bool_arg = (rtx_equal_p (mfvsr_d, bool_a1) ? bool_a2 : bool_a1);\n+ int regno_mfvsr_a = REGNO (operands[SFBOOL2_MFVSR_A]);\n+ int regno_tmp_vsx = REGNO (operands[SFBOOL2_TMP_VSX_V4SI]);\n+\n+ /* If the logical operation is a constant, form the constant in a vector\n+ register. */\n+ if (CONST_INT_P (bool_arg))\n+ {\n+ HOST_WIDE_INT value = INTVAL (bool_arg);\n+\n+ /* See if we can directly load the constant, either by VSPLTIW or by\n+ XXSPLTIW on power10. */\n+\n+ if (IN_RANGE (value, -16, 15) || TARGET_PREFIXED)\n+\t{\n+\t rtvec cv = gen_rtvec (4, bool_arg, bool_arg, bool_arg, bool_arg);\n+\t operands[SFBOOL2_MTVSR_D] = gen_rtx_REG (V4SImode, regno_tmp_vsx);\n+\t operands[SFBOOL2_MTVSR_A] = gen_rtx_CONST_VECTOR (V4SImode, cv);\n+\t}\n+\n+ else\n+\t{\n+\t /* We need to load up the constant to a GPR and move it to a\n+\t vector register. */\n+\t rtx tmp_gpr = operands[SFBOOL2_TMP_GPR_SI];\n+\t emit_move_insn (tmp_gpr, bool_arg);\n+\t operands[SFBOOL2_MTVSR_D] = gen_rtx_REG (SImode, regno_tmp_vsx);\n+\t operands[SFBOOL2_MTVSR_A] = tmp_gpr;\n+\t}\n+ }\n+ else\n+ {\n+ /* Mask is in a register, move it to a vector register. */\n+ operands[SFBOOL2_MTVSR_D] = gen_rtx_REG (SImode, regno_tmp_vsx);\n+ operands[SFBOOL2_MTVSR_A] = bool_arg;\n+ }\n+\n+ operands[SFBOOL2_TMP_VSX_V4SI] = gen_rtx_REG (V4SImode, regno_tmp_vsx);\n+ operands[SFBOOL2_MFVSR_A_V4SI] = gen_rtx_REG (V4SImode, regno_mfvsr_a);\n+ operands[SFBOOL2_XXSPLTW] = GEN_INT (BYTES_BIG_ENDIAN ? 1 : 2);\n+})\n+\n ;; Support signed/unsigned long long to float conversion vectorization.\n ;; Note that any_float (pc) here is just for code attribute <su>.\n (define_expand \"vec_pack<su>_float_v2di\"\ndiff --git a/gcc/testsuite/gcc.target/powerpc/pr117487.c b/gcc/testsuite/gcc.target/powerpc/pr117487.c\nnew file mode 100644\nindex 00000000000..80d2bc16914\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/pr117487.c\n@@ -0,0 +1,67 @@\n+/* { dg-do compile { target lp64 } } */\n+/* { dg-options \"-mdejagnu-cpu=power9 -O2\" } */\n+/* { dg-require-effective-target powerpc_vsx } */\n+\n+#include <stdint.h>\n+\n+/*\n+ * PR target/117487\n+ *\n+ * On power8 with the optimization it generates:\n+ *\n+ *\txscvdpspn 0,1\n+ *\tsldi 9,4,32\n+ *\tmtvsrd 32,9\n+ *\txxland 1,0,32\n+ *\txscvspdpn 1,1\n+ *\n+ * I.e., it converts the SFmode to the memory format (instead of the DFmode\n+ * that is used within the register), converts the mask so that it is in the\n+ * vector register in the upper 32-bits, and does a XXLAND (i.e. there is only\n+ * one direct move from GPR to vector register). Then after doing this, it\n+ * converts the upper 32-bits back to DFmode.\n+ *\n+ * If the XSCVSPDN instruction took the value in the normal 32-bit scalar in a\n+ * vector register, we wouldn't have needed the SLDI of the mask.\n+ *\n+ * On power9/power10/power11 before the fix wa applied, GCC generated:\n+ *\n+ *\txscvdpspn 0,1\n+ *\tmfvsrwz 2,0\n+ *\tand 2,2,4\n+ *\tmtvsrws 1,2\n+ *\txscvspdpn 1,1\n+ *\tblr\n+ *\n+ * I.e convert to SFmode representation, move the value to a GPR, do an AND\n+ * operation, move the 32-bit value with a splat, and then convert it back to\n+ * DFmode format.\n+ *\n+ * After the patch was applied, it now generates:\n+ *\n+ *\txscvdpspn 0,1\n+ *\tmtvsrwz 32,2\n+ *\txxland 32,0,32\n+ *\txxspltw 1,32,1\n+ *\txscvspdpn 1,1\n+ *\tblr\n+ */\n+\n+union u {\n+ float f;\n+ uint32_t u32;\n+};\n+\n+float\n+math_foo (float x, unsigned int mask)\n+{\n+ union u arg;\n+\n+ arg.f = x;\n+ arg.u32 &= mask;\n+ return arg.f;\n+}\n+\n+/* { dg-final { scan-assembler {\\mxxland\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mmfvsr} } } */\n+/* { dg-final { scan-assembler-not {\\mand\\M} } } */\n", "prefixes": [] }