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{
    "id": 2225237,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225237/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260420152529.687075-1-mnissler@meta.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20260420152529.687075-1-mnissler@meta.com>",
    "date": "2026-04-20T15:25:29",
    "name": "[pciutils] Update DPC tests/cap-dpc",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "16f4613c058f0ef288e13efd499210da827acedb",
    "submitter": {
        "id": 93169,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/93169/?format=api",
        "name": "Mattias Nissler",
        "email": "mnissler@meta.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260420152529.687075-1-mnissler@meta.com/mbox/",
    "series": [
        {
            "id": 500644,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/500644/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500644",
            "date": "2026-04-20T15:25:29",
            "name": "[pciutils] Update DPC tests/cap-dpc",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/500644/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2225237/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2225237/checks/",
    "tags": {},
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        "From": "Mattias Nissler <mnissler@meta.com>",
        "To": "<linux-pci@vger.kernel.org>",
        "CC": "=?utf-8?q?Martin_Mare=C5=A1?= <mj@ucw.cz>,\n Mattias Nissler <mnissler@meta.com>",
        "Subject": "[PATCH] [pciutils] Update DPC tests/cap-dpc",
        "Date": "Mon, 20 Apr 2026 08:25:29 -0700",
        "Message-ID": "<20260420152529.687075-1-mnissler@meta.com>",
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    },
    "content": "This adds an ECAM dump from an AMD Bergamo root port that contains\nexemplary DPC RP PIO register contents. Note that I chose to replace the\nexisting file rather than adding a new one. This is because the hex dump\nin the existing file didn't include ECAM data at all, so it wasn't\nactually useful to verify DPC decoding behavior.\n\nSigned-off-by: Mattias Nissler <mnissler@meta.com>\n---\n tests/cap-dpc | 441 +++++++++++++++++++++++++++++++++++++++++---------\n 1 file changed, 365 insertions(+), 76 deletions(-)",
    "diff": "diff --git a/tests/cap-dpc b/tests/cap-dpc\nindex abf37b5..d600efd 100644\n--- a/tests/cap-dpc\n+++ b/tests/cap-dpc\n@@ -1,91 +1,380 @@\n-05:01.0 Class 0604: Device 10b5:9716 (rev aa)\n-\tControl: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+\n+00:01.1 Class 0604: Device 1022:14ab (rev 01)\n+\tSubsystem: Device 1022:1453\n+\tControl: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+\n \tStatus: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-\n-\tLatency: 0, Cache Line Size: 32 bytes\n-\tInterrupt: pin A routed to IRQ 46\n-\tNUMA node: 0\n-\tBus: primary=05, secondary=06, subordinate=06, sec-latency=0\n-\tI/O behind bridge: 0000f000-00000fff\n-\tMemory behind bridge: c6c00000-c6ffffff\n-\tPrefetchable memory behind bridge: 0000383ff9c00000-0000383ff9ffffff\n+\tLatency: 0, Cache Line Size: 64 bytes\n+\tBus: primary=00, secondary=01, subordinate=0c, sec-latency=0\n+\tI/O behind bridge: 0000f000-00000fff [disabled] [32-bit]\n+\tMemory behind bridge: f7000000-f7dfffff [size=14M] [32-bit]\n+\tPrefetchable memory behind bridge: 0000180000000000-00001960042fffff [size=1441859M] [64-bit]\n \tSecondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-\n-\tBridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-\n+\tBridgeCtl: Parity- SERR+ NoISA- VGA- VGA16+ MAbort- >Reset- FastB2B-\n \t\tPriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-\n-\tCapabilities: [40] Power Management version 3\n+\tCapabilities: [48] Vendor Specific Information: Len=08 <?>\n+\tCapabilities: [50] Power Management version 3\n \t\tFlags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)\n-\t\tStatus: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-\n-\tCapabilities: [48] MSI: Enable+ Count=1/8 Maskable+ 64bit+\n-\t\tAddress: 00000000fee004d8  Data: 0000\n-\t\tMasking: 000000fe  Pending: 00000000\n-\tCapabilities: [68] Express (v2) Downstream Port (Slot+), MSI 00\n-\t\tDevCap:\tMaxPayload 1024 bytes, PhantFunc 0\n-\t\t\tExtTag- RBE+\n-\t\tDevCtl:\tReport errors: Correctable- Non-Fatal- Fatal- Unsupported-\n-\t\t\tRlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+\n-\t\t\tMaxPayload 128 bytes, MaxReadReq 128 bytes\n-\t\tDevSta:\tCorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-\n-\t\tLnkCap:\tPort #1, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L0s <4us, L1 <4us\n+\t\tStatus: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-\n+\tCapabilities: [58] Express (v2) Root Port (Slot+), IntMsgNum 0\n+\t\tDevCap:\tMaxPayload 512 bytes, PhantFunc 0\n+\t\t\tExtTag+ RBE+ TEE-IO-\n+\t\tDevCtl:\tCorrErr+ NonFatalErr+ FatalErr+ UnsupReq-\n+\t\t\tRlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+\n+\t\t\tMaxPayload 512 bytes, MaxReadReq 4096 bytes\n+\t\tDevSta:\tCorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-\n+\t\tLnkCap:\tPort #0, Speed 32GT/s, Width x16, ASPM L1, Exit Latency L1 <64us\n \t\t\tClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+\n-\t\tLnkCtl:\tASPM Disabled; Disabled- CommClk-\n-\t\t\tExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-\n-\t\tLnkSta:\tSpeed 8GT/s, Width x4, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt-\n-\t\tSltCap:\tAttnBtn- PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise+\n-\t\t\tSlot #1, PowerLimit 25.000W; Interlock- NoCompl-\n-\t\tSltCtl:\tEnable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+\n+\t\tLnkCtl:\tASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+\n+\t\t\tExtSynch- ClockPM- AutWidDis- BWInt+ AutBWInt+ FltModeDis-\n+\t\tLnkSta:\tSpeed 32GT/s, Width x16\n+\t\t\tTrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-\n+\t\tSltCap:\tAttnBtn+ PwrCtrl+ MRL- AttnInd+ PwrInd+ HotPlug+ Surprise-\n+\t\t\tSlot #327, PowerLimit 75W; Interlock+ NoCompl-\n+\t\tSltCtl:\tEnable: AttnBtn+ PwrFlt- MRL- PresDet- CmdCplt+ HPIrq+ LinkChg+\n \t\t\tControl: AttnInd Off, PwrInd On, Power- Interlock-\n \t\tSltSta:\tStatus: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-\n \t\t\tChanged: MRL- PresDet- LinkState-\n-\t\tDevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via message ARIFwd+\n-\t\tDevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd+\n-\t\tLnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB\n+\t\tRootCap: CRSVisible+\n+\t\tRootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible+\n+\t\tRootSta: PME ReqID 0000, PMEStatus- PMEPending-\n+\t\tDevCap2: Completion Timeout: Range ABCD, TimeoutDis+ NROPrPrP- LTR+\n+\t\t\t 10BitTagComp+ 10BitTagReq+ OBFF Via message/WAKE#, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1\n+\t\t\t EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-\n+\t\t\t FRS- LN System CLS Not Supported, TPHComp+ ExtTPHComp- ARIFwd+\n+\t\t\t AtomicOpsCap: Routing+ 32bit+ 64bit+ 128bitCAS-\n+\t\tDevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd-\n+\t\t\t AtomicOpsCtl: ReqEn- EgressBlck-\n+\t\t\t IDOReq+ IDOCompl+ LTR- EmergencyPowerReductionReq-\n+\t\t\t 10BitTagReq- OBFF Disabled, EETLPPrefixBlk-\n+\t\tLnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-\n+\t\tLnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis-\n \t\t\t Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-\n-\t\t\t Compliance De-emphasis: -6dB\n-\t\tLnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+\n-\t\t\t EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest-\n-\tCapabilities: [a4] Subsystem: Device 10b5:9716\n-\tCapabilities: [100 v1] Device Serial Number 00-0e-df-10-b5-97-00-aa\n-\tCapabilities: [fb4 v1] Advanced Error Reporting\n-\t\tUESta:\tDLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\n-\t\tUEMsk:\tDLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-\n-\t\tUESvrt:\tDLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-\n-\t\tCESta:\tRxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-\n-\t\tCEMsk:\tRxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+\n-\t\tAERCap:\tFirst Error Pointer: 1f, GenCap+ CGenEn- ChkCap+ ChkEn-\n-\tCapabilities: [138 v1] Power Budgeting <?>\n-\tCapabilities: [10c v1] #19\n-\tCapabilities: [148 v1] Virtual Channel\n-\t\tCaps:\tLPEVC=0 RefClk=100ns PATEntryBits=1\n-\t\tArb:\tFixed- WRR32- WRR64- WRR128-\n-\t\tCtrl:\tArbSelect=Fixed\n-\t\tStatus:\tInProgress-\n-\t\tVC0:\tCaps:\tPATOffset=00 MaxTimeSlots=1 RejSnoopTrans-\n-\t\t\tArb:\tFixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-\n-\t\t\tCtrl:\tEnable+ ID=0 ArbSelect=Fixed TC/VC=01\n-\t\t\tStatus:\tNegoPending- InProgress-\n-\tCapabilities: [f24 v1] Access Control Services\n-\t\tACSCap:\tSrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl+ DirectTrans+\n-\t\tACSCtl:\tSrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-\n-\tCapabilities: [b70 v1] Vendor Specific Information: ID=0001 Rev=0 Len=010 <?>\n-\tCapabilities: [b60 v1] Downstream Port Containment\n-\t\tDpcCap:\tINT Msg #0, RPExt- PoisonedTLP+ SwTrigger+ RP PIO Log 0, DL_ActiveErr+\n-\t\tDpcCtl:\tTrigger:2 Cmpl+ INT+ ErrCor- PoisonedTLP- SwTrigger- DL_ActiveErr-\n-\t\tDpcSta:\tTrigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:00\n+\t\t\t Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot\n+\t\tLnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+\n+\t\t\t EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest-\n+\t\t\t Retimer+ 2Retimers- CrosslinkRes: unsupported, FltMode-\n+\tCapabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+\n+\t\tAddress: 00000000fee00000  Data: 0000\n+\tCapabilities: [c0] Subsystem: Device 1022:1453\n+\tCapabilities: [c8] HyperTransport: MSI Mapping Enable+ Fixed+\n+\tCapabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>\n+\tCapabilities: [150 v2] Advanced Error Reporting\n+\t\tUESta:\tDLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP-\n+\t\t\tECRC- UnsupReq- ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr-\n+\t\t\tPoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-\n+\t\tUEMsk:\tDLP- SDES+ TLP- FCP- CmpltTO+ CmpltAbrt- UnxCmplt- RxOF- MalfTLP-\n+\t\t\tECRC- UnsupReq+ ACSViol- UncorrIntErr- BlockedTLP- AtomicOpBlocked- TLPBlockedErr-\n+\t\t\tPoisonTLPBlocked- DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-\n+\t\tUESvrt:\tDLP+ SDES+ TLP+ FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+\n+\t\t\tECRC+ UnsupReq- ACSViol- UncorrIntErr+ BlockedTLP- AtomicOpBlocked- TLPBlockedErr+\n+\t\t\tPoisonTLPBlocked+ DMWrReqBlocked- IDECheck- MisIDETLP- PCRC_CHECK- TLPXlatBlocked-\n+\t\tCESta:\tRxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- CorrIntErr- HeaderOF-\n+\t\tCEMsk:\tRxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ CorrIntErr- HeaderOF-\n+\t\tAERCap:\tFirst Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn+\n+\t\t\tMultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-\n+\t\tHeaderLog: 00000000 00000000 00000000 00000000\n+\t\tRootCmd: CERptEn- NFERptEn- FERptEn-\n+\t\tRootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-\n+\t\t\t FirstFatal- NonFatalMsg- FatalMsg- IntMsgNum 0\n+\t\tErrorSrc: ERR_COR: 0009 ERR_FATAL/NONFATAL: 0000\n+\tCapabilities: [270 v1] Secondary PCI Express\n+\t\tLnkCtl3: LnkEquIntrruptEn- PerformEqu-\n+\t\tLaneErrStat: 0\n+\tCapabilities: [2a0 v1] Access Control Services\n+\t\tACSCap:\tSrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans+\n+\t\tACSCtl:\tSrcValid+ TransBlk- ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl- DirectTrans-\n+\tCapabilities: [380 v1] Downstream Port Containment\n+\t\tDpcCap:\tIntMsgNum 0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 6, DL_ActiveErr+\n+\t\tDpcCtl:\tTrigger:0 Cmpl+ INT+ ErrCor+ PoisonedTLP- SwTrigger- DL_ActiveErr-\n+\t\tDpcSta:\tTrigger- Reason:00 INT- RPBusy- TriggerExt:00 RP PIO ErrPtr:11\n \t\tSource:\t0000\n-\tKernel driver in use: pcieport\n-00: b5 10 16 97 07 05 10 00 aa 00 04 06 08 00 01 00\n-10: 00 00 00 00 00 00 00 00 05 06 06 00 f1 01 00 00\n-20: c0 c6 f0 c6 c1 f9 f1 f9 3f 38 00 00 3f 38 00 00\n-30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 12 00\n-40: 01 48 03 c8 08 00 00 00 05 68 87 01 d8 04 e0 fe\n-50: 00 00 00 00 00 00 00 00 fe 00 00 00 00 00 00 00\n-60: 00 00 00 00 00 00 00 00 10 a4 62 01 03 80 00 00\n-70: 00 08 09 00 43 68 79 01 00 00 43 60 fa 0c 08 00\n-80: f8 11 40 00 00 00 00 00 00 00 00 00 60 08 04 00\n-90: 20 00 00 00 0e 0f 00 00 03 00 1e 00 00 00 00 00\n-a0: 00 00 00 00 0d 00 00 00 b5 10 16 97 00 00 00 00\n+\t\tRP PIO:\n+\t\t\tSta: CfgUR+ CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA+ MemCTO-\n+\t\t\tMsk: CfgUR+ CfgCA+ CfgCTO+ IOUR+ IOCA+ IOCTO+ MemUR- MemCA- MemCTO-\n+\t\t\tSev: CfgUR- CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA- MemCTO-\n+\t\t\tErr: CfgUR- CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA- MemCTO-\n+\t\t\tExc: CfgUR- CfgCA- CfgCTO- IOUR- IOCA- IOCTO- MemUR- MemCA- MemCTO-\n+\t\t\tHeaderLog: 00001001 0000230f f7801100 00000000\n+\t\t\tImpSpecLog: 00000000\n+\t\t\tTLPPrefixLog: 00000000\n+\tCapabilities: [400 v1] Data Link Feature <?>\n+\tCapabilities: [410 v1] Physical Layer 16.0 GT/s\n+\t\tPhy16Sta: EquComplete+ EquPhase1+ EquPhase2+ EquPhase3+ LinkEquRequest-\n+\tCapabilities: [440 v1] Lane Margining at the Receiver\n+\t\tPortCap: Uses Driver-\n+\t\tPortSta: MargReady+ MargSoftReady-\n+\tCapabilities: [4d0 v1] Native PCIe Enclosure Management <?>\n+\tCapabilities: [500 v1] Physical Layer 32.0 GT/s\n+\t\tPhy32Cap: EqualizationBypass+ NoEqualizationNeeded-\n+\t\t\t  ModTsMode0+ ModTsMode1- ModTsMode2+\n+\t\tPhy32Ctl: EqualizationBypassDis+ NoEqualizationNeededDis-\n+\t\t\t  Modified TS Usage Mode: Alternate Protocol Negotiation\n+\t\tPhy32Sta: EquComplete+ EquPhase1+ EquPhase2+ EquPhase3+ LinkEquRequest-\n+\t\t\t  Received Enhanced Link Behavior Control: Full Equalization required\n+\t\t\t  ModTsRecv- TxPrecodeOn- TxPrecodeReq- NoEqualizationNeededRecv-\n+\tCapabilities: [530 v1] Extended Capability ID 0x2b\n+\tCapabilities: [57c v1] Designated Vendor-Specific: Vendor=1e98 ID=0007 Rev=0 Len=16: CXL\n+\t\tPCIe DVSEC for Flex Bus Port\n+\t\tFBCap:\tCache+ IO+ Mem+ 68BFlit- MltLogDev-\n+\t\tFBCtl:\tCache+ IO+ Mem+ SynHdrByp- DrftBuf- 68BFlit- MltLogDev- RCD- Retimer1- Retimer2-\n+\t\tFBSta:\tCache- IO- Mem- SynHdrByp- DrftBuf- 68BFlit- MltLogDev-\n+\tCapabilities: [5f4 v1] Designated Vendor-Specific: Vendor=1e98 ID=0004 Rev=0 Len=16: CXL\n+\t\tGPF DVSEC for CXL Ports\n+\t\tGPF Phase 1 Timeout: 0us\n+\t\tGPF Phase 2 Timeout: 0us\n+00: 22 10 ab 14 07 04 10 00 01 00 04 06 10 00 81 00\n+10: 00 00 00 00 00 00 00 00 00 01 0c 00 f1 01 00 00\n+20: 00 f7 d0 f7 01 00 21 04 00 18 00 00 60 19 00 00\n+30: 00 00 00 00 48 00 00 00 00 00 00 00 ff 00 12 00\n+40: 00 00 00 00 00 00 00 00 09 50 08 00 22 10 53 14\n+50: 01 58 03 c8 00 00 00 00 10 a0 42 01 22 80 00 00\n+60: 57 59 00 00 05 79 7b 00 40 0c 05 31 db 25 3a 0a\n+70: f1 11 40 00 10 00 01 00 00 00 00 00 ff 19 7f 00\n+80: 06 03 00 00 3e 00 80 01 05 00 5e 00 01 00 00 00\n+90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a0: 05 c0 81 00 00 00 e0 fe 00 00 00 00 00 00 00 00\n b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n-c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+c0: 0d c8 00 00 22 10 53 14 08 00 03 a8 00 00 00 00\n d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+100: 0b 00 01 15 01 00 01 01 00 00 00 00 00 00 00 00\n+110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+150: 01 00 02 27 00 00 00 00 20 40 10 00 30 30 4e 06\n+160: 00 00 00 00 00 20 00 00 a0 01 00 00 00 00 00 00\n+170: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+180: 00 00 00 00 09 00 00 00 00 00 00 00 00 00 00 00\n+190: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+1a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+1b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+1c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+1d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+1e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+1f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+270: 19 00 01 2a 00 00 00 00 00 00 00 00 37 34 37 34\n+280: 37 34 37 34 37 34 37 34 37 34 37 34 37 34 37 34\n+290: 37 34 37 34 37 34 37 34 37 34 37 34 00 00 00 00\n+2a0: 0d 00 01 38 5f 00 1d 00 00 00 00 00 00 00 00 00\n+2b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+2c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+2d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+2e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+2f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+310: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+370: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+380: 1d 00 01 40 e0 16 1c 00 00 11 00 00 01 00 02 00\n+390: 07 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+3a0: 01 10 00 00 0f 23 00 00 00 11 80 f7 00 00 00 00\n+3b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+3c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+3d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+3e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+3f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+400: 25 00 01 41 01 00 00 80 01 00 00 80 00 00 00 00\n+410: 26 00 01 44 00 00 00 00 00 00 00 00 0f 00 00 00\n+420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+430: 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47\n+440: 27 00 01 4d 00 00 01 00 0a 8f 0a 00 0a 8f 0a 00\n+450: 0a 8f 0a 00 0a 8f 0a 00 0a 8f 0a 00 0a 8f 0a 00\n+460: 0a 8f 0a 00 0a 8f 0a 00 0a 8f 0a 00 0a 8f 0a 00\n+470: 0a 8f 0a 00 0a 8f 0a 00 0a 8f 0a 00 0a 8f 0a 00\n+480: 0a 8f 0a 00 0a 8f 0a 00 00 00 00 00 00 00 00 00\n+490: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+4a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+4b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+4c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+4d0: 29 00 01 50 00 00 00 00 00 00 00 00 00 00 00 00\n+4e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+4f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+500: 2a 00 01 53 01 05 00 00 01 02 00 00 0f 00 00 00\n+510: 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 01\n+520: 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87 87\n+530: 2b 00 c1 57 02 01 00 00 00 01 00 00 00 00 00 00\n+540: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00\n+550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+570: 00 00 00 00 00 00 00 00 00 00 00 00 23 00 41 5f\n+580: 98 1e 00 01 07 00 07 00 07 00 00 00 00 00 00 00\n+590: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+5a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+5b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+5c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+5d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+5e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+5f0: 00 00 00 00 23 00 01 00 98 1e 00 01 04 00 00 00\n+600: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+610: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+620: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+630: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+640: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+650: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+660: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+670: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+680: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+690: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+6a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+6b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+6c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+6d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+6e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+6f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+700: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+710: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+720: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+730: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+740: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+750: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+760: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+770: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+780: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+790: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+7a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+7b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+7c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+7d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+7e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+7f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+800: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+810: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+820: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+830: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+840: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+870: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+880: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+890: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+8a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+8b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+8c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+8d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+8e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+8f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+900: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+910: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+920: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+930: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+940: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+950: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+960: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+970: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+980: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+990: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+9a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+9b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+9c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+9d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+9e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+9f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+a90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+aa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+ab0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+ac0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+ad0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+ae0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+af0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00\n+b90: 00 00 00 00 00 00 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    "prefixes": [
        "pciutils"
    ]
}