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GET /api/1.1/patches/2225205/?format=api
{ "id": 2225205, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225205/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260420-fix-eliza-pinctrl-v2-2-b68329fd6701@pm.me/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260420-fix-eliza-pinctrl-v2-2-b68329fd6701@pm.me>", "date": "2026-04-20T14:28:04", "name": "[v2,2/2] pinctrl: qcom: eliza: Split up some QUP pin groups", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e915366161b0d03ba833319c640445aaaad1b879", "submitter": { "id": 93184, "url": "http://patchwork.ozlabs.org/api/1.1/people/93184/?format=api", "name": "Alexander Koskovich", "email": "akoskovich@pm.me" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260420-fix-eliza-pinctrl-v2-2-b68329fd6701@pm.me/mbox/", "series": [ { "id": 500622, "url": "http://patchwork.ozlabs.org/api/1.1/series/500622/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=500622", "date": "2026-04-20T14:27:46", "name": "pinctrl: qcom: eliza: Split up some QUP pin groups", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500622/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225205/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225205/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35274-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=pm.me 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legolas.ozlabs.org (Postfix) with ESMTPS id 4fzqw16WLPz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 02:00:49 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 4354F31F5592\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 20 Apr 2026 15:06:11 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 683B43D1CDB;\n\tMon, 20 Apr 2026 14:28:19 +0000 (UTC)", "from mail-244121.protonmail.ch (mail-244121.protonmail.ch\n [109.224.244.121])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 387EA3D1CC5;\n\tMon, 20 Apr 2026 14:28:17 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776695299; cv=none;\n b=RLRkF68N8hr1qV5nvDFcpcLbNAL1Owr2hXi3c9vsAoImzWC4eJFWBsuDEsenV1zqKIsB+7do+9G7OuyVOxIx4zouqWSx2uGeMSZ3rw7AWAQBsPtSnAaiu4zeYqxQDEUedrdtcbPD8+ZHQTT/e91421ILo8a1ZkQgqdX9cT1+EbI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776695299; c=relaxed/simple;\n\tbh=9tLbAL/IkJ8RXG3NKCcoFK7v5tgajuxUZOxxl45bQkw=;\n\th=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=e+CFHx2mpXjubuDO+wifjEV+FM1ixBX+4F9mkerxlJ1tGIP2MNQvHMC/0iqMZoHgi5F2+zaM7M7pDW6mFQmV4h4N/AT+jdmT+kaGWeTA0rmyJG+VY+B4cxxM+dGx7jqVHDcz7V256RoKtyfjIXnz91l4eMzlegqNz6bwdfkVneY=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=pm.me;\n spf=pass smtp.mailfrom=pm.me;\n dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=VyICU1GJ;\n arc=none smtp.client-ip=109.224.244.121", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me;\n\ts=protonmail3; t=1776695289; x=1776954489;\n\tbh=9tLbAL/IkJ8RXG3NKCcoFK7v5tgajuxUZOxxl45bQkw=;\n\th=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References:\n\t Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID:\n\t Message-ID:BIMI-Selector;\n\tb=VyICU1GJvjK/5vXjR/YBEZDqfpfOpG4BBXTAD9X6a7UdyoXGwmqi26e45zuxngyd7\n\t oksq9WfdOl/gKg+EhmcCKNilCTrMBFsQdpggmk288VdAnYEz6nAZX7SN/8reNrZ+BO\n\t CTnyZ5Mbg8py+06oZ+P22BWRgqBYa8gRDAa7Zidrojtoxn6nYXu3nLYe/QICKm1EVQ\n\t Rsr4IBNusLiVdR4Wx8uUjsFRQ+8UNZmA2pp1gdJMUad/JZD8gLRzvdWzWPDQLbWXbp\n\t knwXbLcCS/i1fwVJF6WQgJFJ7ORsq0zbaQWkVFf/H95Ow3Pbk/MczGyZhLrqkeYy9O\n\t PnhXRB4/eT/FQ==", "Date": "Mon, 20 Apr 2026 14:28:04 +0000", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Abel Vesa <abel.vesa@oss.qualcomm.com>", "From": "Alexander Koskovich <akoskovich@pm.me>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Alexander Koskovich <akoskovich@pm.me>", "Subject": "[PATCH v2 2/2] pinctrl: qcom: eliza: Split up some QUP pin groups", "Message-ID": "<20260420-fix-eliza-pinctrl-v2-2-b68329fd6701@pm.me>", "In-Reply-To": "<20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me>", "References": "<20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me>", "Feedback-ID": "37836894:user:proton", "X-Pm-Message-ID": "0b36d055a9c635361ef9d952bdef044d3e7cad8a", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=utf-8", "Content-Transfer-Encoding": "quoted-printable" }, "content": "Multiple QUPs have lanes that can be routed to one of two GPIOs and\ncollapsing them prevents devicetrees from requesting specific routing.\n\nFor example, a board that wires an I2C SCL line to one of two GPIOs\ncannot request that specific pin with the groups collapsed.\n\nThis change splits them up so devicetrees can request the configuration\nthey need.\n\nSigned-off-by: Alexander Koskovich <akoskovich@pm.me>\n---\n drivers/pinctrl/qcom/pinctrl-eliza.c | 200 +++++++++++++++++++++++++++++------\n 1 file changed, 169 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c\nindex c1f756cbcdeb..a1365bcd3bf6 100644\n--- a/drivers/pinctrl/qcom/pinctrl-eliza.c\n+++ b/drivers/pinctrl/qcom/pinctrl-eliza.c\n@@ -562,16 +562,39 @@ enum eliza_functions {\n \tmsm_mux_qspi_cs,\n \tmsm_mux_qup1_se0,\n \tmsm_mux_qup1_se1,\n-\tmsm_mux_qup1_se2,\n+\tmsm_mux_qup1_se2_l0,\n+\tmsm_mux_qup1_se2_l1,\n+\tmsm_mux_qup1_se2_l2_mira,\n+\tmsm_mux_qup1_se2_l2_mirb,\n+\tmsm_mux_qup1_se2_l3_mira,\n+\tmsm_mux_qup1_se2_l3_mirb,\n+\tmsm_mux_qup1_se2_l4,\n+\tmsm_mux_qup1_se2_l5,\n+\tmsm_mux_qup1_se2_l6,\n \tmsm_mux_qup1_se3,\n \tmsm_mux_qup1_se4,\n \tmsm_mux_qup1_se5,\n-\tmsm_mux_qup1_se6,\n-\tmsm_mux_qup1_se7,\n+\tmsm_mux_qup1_se6_l0,\n+\tmsm_mux_qup1_se6_l1_mira,\n+\tmsm_mux_qup1_se6_l1_mirb,\n+\tmsm_mux_qup1_se6_l2,\n+\tmsm_mux_qup1_se6_l3_mira,\n+\tmsm_mux_qup1_se6_l3_mirb,\n+\tmsm_mux_qup1_se7_l0_mira,\n+\tmsm_mux_qup1_se7_l0_mirb,\n+\tmsm_mux_qup1_se7_l1_mira,\n+\tmsm_mux_qup1_se7_l1_mirb,\n+\tmsm_mux_qup1_se7_l2,\n+\tmsm_mux_qup1_se7_l3,\n \tmsm_mux_qup2_se0,\n \tmsm_mux_qup2_se1,\n \tmsm_mux_qup2_se2,\n-\tmsm_mux_qup2_se3,\n+\tmsm_mux_qup2_se3_l0_mira,\n+\tmsm_mux_qup2_se3_l0_mirb,\n+\tmsm_mux_qup2_se3_l1_mira,\n+\tmsm_mux_qup2_se3_l1_mirb,\n+\tmsm_mux_qup2_se3_l2,\n+\tmsm_mux_qup2_se3_l3,\n \tmsm_mux_qup2_se4,\n \tmsm_mux_qup2_se5,\n \tmsm_mux_qup2_se6,\n@@ -977,8 +1000,40 @@ static const char *const qup1_se1_groups[] = {\n \t\"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n };\n \n-static const char *const qup1_se2_groups[] = {\n-\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio52\", \"gpio55\", \"gpio53\", \"gpio40\", \"gpio42\", \"gpio30\",\n+static const char *const qup1_se2_l0_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const qup1_se2_l1_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const qup1_se2_l2_mira_groups[] = {\n+\t\"gpio54\",\n+};\n+\n+static const char *const qup1_se2_l2_mirb_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const qup1_se2_l3_mira_groups[] = {\n+\t\"gpio55\",\n+};\n+\n+static const char *const qup1_se2_l3_mirb_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const qup1_se2_l4_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char *const qup1_se2_l5_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const qup1_se2_l6_groups[] = {\n+\t\"gpio30\",\n };\n \n static const char *const qup1_se3_groups[] = {\n@@ -993,12 +1048,52 @@ static const char *const qup1_se5_groups[] = {\n \t\"gpio132\", \"gpio133\", \"gpio134\", \"gpio135\", \"gpio34\", \"gpio35\",\n };\n \n-static const char *const qup1_se6_groups[] = {\n-\t\"gpio40\", \"gpio42\", \"gpio54\", \"gpio42\", \"gpio40\", \"gpio55\",\n+static const char *const qup1_se6_l0_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char *const qup1_se6_l1_mira_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const qup1_se6_l1_mirb_groups[] = {\n+\t\"gpio54\",\n+};\n+\n+static const char *const qup1_se6_l2_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const qup1_se6_l3_mira_groups[] = {\n+\t\"gpio40\",\n };\n \n-static const char *const qup1_se7_groups[] = {\n-\t\"gpio81\", \"gpio78\", \"gpio80\", \"gpio114\", \"gpio114\", \"gpio78\",\n+static const char *const qup1_se6_l3_mirb_groups[] = {\n+\t\"gpio55\",\n+};\n+\n+static const char *const qup1_se7_l0_mira_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const char *const qup1_se7_l0_mirb_groups[] = {\n+\t\"gpio78\",\n+};\n+\n+static const char *const qup1_se7_l1_mira_groups[] = {\n+\t\"gpio80\",\n+};\n+\n+static const char *const qup1_se7_l1_mirb_groups[] = {\n+\t\"gpio114\",\n+};\n+\n+static const char *const qup1_se7_l2_groups[] = {\n+\t\"gpio114\",\n+};\n+\n+static const char *const qup1_se7_l3_groups[] = {\n+\t\"gpio78\",\n };\n \n static const char *const qup2_se0_groups[] = {\n@@ -1013,8 +1108,28 @@ static const char *const qup2_se2_groups[] = {\n \t\"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio16\", \"gpio17\", \"gpio18\",\n };\n \n-static const char *const qup2_se3_groups[] = {\n-\t\"gpio79\", \"gpio116\", \"gpio97\", \"gpio100\", \"gpio100\", \"gpio116\",\n+static const char *const qup2_se3_l0_mira_groups[] = {\n+\t\"gpio79\",\n+};\n+\n+static const char *const qup2_se3_l0_mirb_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const qup2_se3_l1_mira_groups[] = {\n+\t\"gpio97\",\n+};\n+\n+static const char *const qup2_se3_l1_mirb_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const qup2_se3_l2_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const qup2_se3_l3_groups[] = {\n+\t\"gpio116\",\n };\n \n static const char *const qup2_se4_groups[] = {\n@@ -1235,16 +1350,39 @@ static const struct pinfunction eliza_functions[] = {\n \tMSM_PIN_FUNCTION(qspi_cs),\n \tMSM_PIN_FUNCTION(qup1_se0),\n \tMSM_PIN_FUNCTION(qup1_se1),\n-\tMSM_PIN_FUNCTION(qup1_se2),\n+\tMSM_PIN_FUNCTION(qup1_se2_l0),\n+\tMSM_PIN_FUNCTION(qup1_se2_l1),\n+\tMSM_PIN_FUNCTION(qup1_se2_l2_mira),\n+\tMSM_PIN_FUNCTION(qup1_se2_l2_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se2_l3_mira),\n+\tMSM_PIN_FUNCTION(qup1_se2_l3_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se2_l4),\n+\tMSM_PIN_FUNCTION(qup1_se2_l5),\n+\tMSM_PIN_FUNCTION(qup1_se2_l6),\n \tMSM_PIN_FUNCTION(qup1_se3),\n \tMSM_PIN_FUNCTION(qup1_se4),\n \tMSM_PIN_FUNCTION(qup1_se5),\n-\tMSM_PIN_FUNCTION(qup1_se6),\n-\tMSM_PIN_FUNCTION(qup1_se7),\n+\tMSM_PIN_FUNCTION(qup1_se6_l0),\n+\tMSM_PIN_FUNCTION(qup1_se6_l1_mira),\n+\tMSM_PIN_FUNCTION(qup1_se6_l1_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se6_l2),\n+\tMSM_PIN_FUNCTION(qup1_se6_l3_mira),\n+\tMSM_PIN_FUNCTION(qup1_se6_l3_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se7_l0_mira),\n+\tMSM_PIN_FUNCTION(qup1_se7_l0_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se7_l1_mira),\n+\tMSM_PIN_FUNCTION(qup1_se7_l1_mirb),\n+\tMSM_PIN_FUNCTION(qup1_se7_l2),\n+\tMSM_PIN_FUNCTION(qup1_se7_l3),\n \tMSM_PIN_FUNCTION(qup2_se0),\n \tMSM_PIN_FUNCTION(qup2_se1),\n \tMSM_PIN_FUNCTION(qup2_se2),\n-\tMSM_PIN_FUNCTION(qup2_se3),\n+\tMSM_PIN_FUNCTION(qup2_se3_l0_mira),\n+\tMSM_PIN_FUNCTION(qup2_se3_l0_mirb),\n+\tMSM_PIN_FUNCTION(qup2_se3_l1_mira),\n+\tMSM_PIN_FUNCTION(qup2_se3_l1_mirb),\n+\tMSM_PIN_FUNCTION(qup2_se3_l2),\n+\tMSM_PIN_FUNCTION(qup2_se3_l3),\n \tMSM_PIN_FUNCTION(qup2_se4),\n \tMSM_PIN_FUNCTION(qup2_se5),\n \tMSM_PIN_FUNCTION(qup2_se6),\n@@ -1316,7 +1454,7 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[27] = PINGROUP(27, qup2_se4, aoss_cti, mdp_vsync11_out, qup2_se7, gcc_gp1, _, _, _, _, _, _),\n \t[28] = PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n \t[29] = PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio),\n-\t[30] = PINGROUP(30, qup1_se0, qup1_se2, cci_async_in, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, egpio),\n+\t[30] = PINGROUP(30, qup1_se0, qup1_se2_l6, cci_async_in, gcc_gp3, qdss_gpio_tracedata, _, _, _, _, _, egpio),\n \t[31] = PINGROUP(31, qup1_se0, cci_async_in, qdss_gpio_tracedata, _, _, _, _, _, _, _, egpio),\n \t[32] = PINGROUP(32, qup1_se1, ibi_i3c, audio_ref_clk, gcc_gp2, qdss_cti, _, _, _, _, _, _),\n \t[33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),\n@@ -1326,9 +1464,9 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),\n \t[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),\n \t[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),\n-\t[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),\n+\t[40] = PINGROUP(40, qup1_se6_l0, qup1_se2_l4, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),\n \t[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),\n-\t[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),\n+\t[42] = PINGROUP(42, qup1_se6_l2, qup1_se2_l5, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),\n \t[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),\n \t[44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),\n \t[45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),\n@@ -1338,10 +1476,10 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),\n \t[50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),\n \t[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),\n-\t[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),\n-\t[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),\n-\t[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),\n-\t[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),\n+\t[52] = PINGROUP(52, qup1_se2_l0, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),\n+\t[53] = PINGROUP(53, qup1_se2_l1, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),\n+\t[54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),\n+\t[55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),\n \t[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),\n \t[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),\n \t[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),\n@@ -1364,10 +1502,10 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),\n \t[76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),\n \t[77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),\n-\t[78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),\n-\t[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),\n-\t[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),\n-\t[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),\n+\t[78] = PINGROUP(78, qup1_se7_l3, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _),\n+\t[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _),\n+\t[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _),\n+\t[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _),\n \t[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),\n \t[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),\n \t[84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),\n@@ -1383,10 +1521,10 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),\n \t[95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),\n \t[96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),\n-\t[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),\n+\t[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _),\n \t[98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),\n \t[99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),\n-\t[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),\n+\t[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3_l2, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _),\n \t[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),\n \t[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),\n \t[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),\n@@ -1400,9 +1538,9 @@ static const struct msm_pingroup eliza_groups[] = {\n \t[111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),\n \t[112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),\n \t[113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),\n-\t[114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n+\t[114] = PINGROUP(114, qup1_se7_l2, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),\n \t[115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),\n-\t[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),\n+\t[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3_l3, qup2_se3_l0_mirb, _, _, _, _, _, _, _),\n \t[117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),\n \t[118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),\n \t[119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),\n", "prefixes": [ "v2", "2/2" ] }