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GET /api/1.1/patches/2225188/?format=api
{ "id": 2225188, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225188/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420-rk3576-pwm-v4-4-421738c7bf28@collabora.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260420-rk3576-pwm-v4-4-421738c7bf28@collabora.com>", "date": "2026-04-20T13:35:22", "name": "[v4,4/5] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4ea6e4217da04efea81c8c34d44a4b7178fe9a5d", "submitter": { "id": 90188, "url": "http://patchwork.ozlabs.org/api/1.1/people/90188/?format=api", "name": "Nicolas Frattaroli", "email": "nicolas.frattaroli@collabora.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420-rk3576-pwm-v4-4-421738c7bf28@collabora.com/mbox/", "series": [ { "id": 500618, "url": "http://patchwork.ozlabs.org/api/1.1/series/500618/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500618", "date": "2026-04-20T13:35:22", "name": "Add Rockchip RK3576 PWM Support Through MFPWM", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500618/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225188/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225188/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pwm+bounces-8647-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com\n header.a=rsa-sha256 header.s=zohomail header.b=jURJ2NzR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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mx.zohomail.com;\n\tdkim=pass header.i=collabora.com;\n\tspf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com;\n\tdmarc=pass header.from=<nicolas.frattaroli@collabora.com>" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1776692176;\n\ts=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com;\n\th=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To;\n\tbh=TSolDDpiDBp7rWjrXiBrHsvEmvUxxGJrGij6jJWU4VQ=;\n\tb=jURJ2NzRayZTpsfx6TxqTo3l7pH/lpQeSyUklDQhO7iNn40S+aERlYZH9rHLCJdX\n\tF18quwxwrx+cDu5VivAsiGJVyXY6apEVlOuMLvvQADmBeZtlf40yQ6ZSZDfFDlzFBwo\n\t7zsBf756385OsUDZV0XAkPCtZOUTtJqi2n1z/2oE=", "From": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>", "Date": "Mon, 20 Apr 2026 15:35:22 +0200", "Subject": "[PATCH v4 4/5] arm64: dts: rockchip: add PWM nodes to RK3576 SoC\n dtsi", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260420-rk3576-pwm-v4-4-421738c7bf28@collabora.com>", "References": "<20260420-rk3576-pwm-v4-0-421738c7bf28@collabora.com>", "In-Reply-To": "<20260420-rk3576-pwm-v4-0-421738c7bf28@collabora.com>", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>,\n Lee Jones <lee@kernel.org>, William Breathitt Gray <wbg@kernel.org>,\n Damon Ding <damon.ding@rock-chips.com>", "Cc": "Nicolas Frattaroli <nicolas.frattaroli@collabora.com>,\n kernel@collabora.com, Jonas Karlman <jonas@kwiboo.se>,\n Alexey Charkov <alchark@gmail.com>, linux-rockchip@lists.infradead.org,\n linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-iio@vger.kernel.org", "X-Mailer": "b4 0.15.2" }, "content": "The RK3576 SoC features three distinct PWM controllers, with variable\nnumbers of channels. Add each channel as a separate node to the SoC's\ndevice tree, as they don't really overlap in register ranges.\n\nSigned-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>\n---\n arch/arm64/boot/dts/rockchip/rk3576.dtsi | 208 +++++++++++++++++++++++++++++++\n 1 file changed, 208 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi\nindex e12a2a0cfb89..55d6b103c329 100644\n--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi\n+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi\n@@ -1032,6 +1032,32 @@ uart1: serial@27310000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm0_2ch_0: pwm@27330000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x27330000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,\n+\t\t\t\t <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm0m0_ch0>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm0_2ch_1: pwm@27331000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x27331000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,\n+\t\t\t\t <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm0m0_ch1>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tpmu: power-management@27380000 {\n \t\t\tcompatible = \"rockchip,rk3576-pmu\", \"syscon\", \"simple-mfd\";\n \t\t\treg = <0x0 0x27380000 0x0 0x800>;\n@@ -2630,6 +2656,188 @@ uart9: serial@2adc0000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm1_6ch_0: pwm@2add0000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2add0000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,\n+\t\t\t\t <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm1m0_ch0>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm1_6ch_1: pwm@2add1000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2add1000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,\n+\t\t\t\t <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm1m0_ch1>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm1_6ch_2: pwm@2add2000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2add2000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,\n+\t\t\t\t <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm1m0_ch2>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm1_6ch_3: pwm@2add3000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2add3000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,\n+\t\t\t\t <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm1m0_ch3>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm1_6ch_4: pwm@2add4000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2add4000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,\n+\t\t\t\t <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm1m0_ch4>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm1_6ch_5: pwm@2add5000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2add5000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,\n+\t\t\t\t <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm1m0_ch5>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_0: pwm@2ade0000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade0000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch0>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_1: pwm@2ade1000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade1000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch1>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_2: pwm@2ade2000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade2000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch2>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_3: pwm@2ade3000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade3000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch3>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_4: pwm@2ade4000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade4000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch4>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_5: pwm@2ade5000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade5000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch5>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_6: pwm@2ade6000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade6000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch6>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpwm2_8ch_7: pwm@2ade7000 {\n+\t\t\tcompatible = \"rockchip,rk3576-pwm\";\n+\t\t\treg = <0x0 0x2ade7000 0x0 0x1000>;\n+\t\t\tclocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,\n+\t\t\t\t <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;\n+\t\t\tclock-names = \"pwm\", \"pclk\", \"osc\", \"rc\";\n+\t\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pwm2m0_ch7>;\n+\t\t\t#pwm-cells = <3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\tsaradc: adc@2ae00000 {\n \t\t\tcompatible = \"rockchip,rk3576-saradc\", \"rockchip,rk3588-saradc\";\n \t\t\treg = <0x0 0x2ae00000 0x0 0x10000>;\n", "prefixes": [ "v4", "4/5" ] }