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GET /api/1.1/patches/2225174/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2225174,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225174/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420140552.104369-5-eric.auger@redhat.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260420140552.104369-5-eric.auger@redhat.com>",
    "date": "2026-04-20T14:03:54",
    "name": "[v10,4/7] target/arm/cpu64: Mitigate migration failures due to spurious TCR_EL1, PIRE0_EL1 and PIR_EL1",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "a78464ae25a22deb3a1f95e2d25c578eb59a069c",
    "submitter": {
        "id": 69187,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/69187/?format=api",
        "name": "Eric Auger",
        "email": "eric.auger@redhat.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420140552.104369-5-eric.auger@redhat.com/mbox/",
    "series": [
        {
            "id": 500612,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/500612/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500612",
            "date": "2026-04-20T14:03:52",
            "name": "[v10,1/7] target/arm/cpu: Introduce the infrastructure for cpreg migration tolerances",
            "version": 10,
            "mbox": "http://patchwork.ozlabs.org/series/500612/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2225174/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2225174/checks/",
    "tags": {},
    "headers": {
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        ],
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        "X-Mimecast-MFC-AGG-ID": "vfXhS75uNo2weegzwuybVQ_1776693978",
        "From": "Eric Auger <eric.auger@redhat.com>",
        "To": "eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org,\n qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com,\n sebott@redhat.com, peterx@redhat.com, philmd@linaro.org,\n alex.bennee@linaro.org",
        "Subject": "[PATCH v10 4/7] target/arm/cpu64: Mitigate migration failures due to\n spurious TCR_EL1, PIRE0_EL1 and PIR_EL1",
        "Date": "Mon, 20 Apr 2026 16:03:54 +0200",
        "Message-ID": "<20260420140552.104369-5-eric.auger@redhat.com>",
        "In-Reply-To": "<20260420140552.104369-1-eric.auger@redhat.com>",
        "References": "<20260420140552.104369-1-eric.auger@redhat.com>",
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    },
    "content": "Before linux v6.13 those registers were erroneously unconditionally\nexposed and this was fixed by commits:\n- 0fcb4eea5345 (\"KVM: arm64: Hide TCR2_EL1 from userspace when\n                 disabled for guests\")\n- a68cddbe47ef (\"KVM: arm64: Hide S1PIE registers from userspace\n                 when disabled for guests\")\nin v6.13.\n\nThis means if we migrate from an old kernel host to a >= 6.13 kernel\nhost, migration currently fails.\n\nDeclare cpreg migration tolerance for those registers.\n\nSigned-off-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Sebastian Ott <sebott@redhat.com>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\n\n---\n\nv9 -> v10\n- Put kvm_arm_set_cpreg_mig_tolerances definition in\n  #if defined(CONFIG_KVM).\n- Added Peter's R-b\n---\n target/arm/cpu64.c | 28 ++++++++++++++++++++++++++++\n 1 file changed, 28 insertions(+)",
    "diff": "diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex d6feba220e8..e7014022df4 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -810,6 +810,33 @@ static void aarch64_a53_initfn(Object *obj)\n     define_cortex_a72_a57_a53_cp_reginfo(cpu);\n }\n \n+#if defined(CONFIG_KVM)\n+static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu)\n+{\n+    /*\n+     * Registers that may be in the incoming stream and not exposed\n+     * on the destination\n+     */\n+\n+    /*\n+     * TCR_EL1 was erroneously unconditionnally exposed before linux v6.13.\n+     * See commit 0fcb4eea5345 (\"KVM: arm64: Hide TCR2_EL1 from userspace\n+     * when disabled for guests\")\n+     */\n+    arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 2, 0, 3),\n+                                     0, 0, ToleranceNotOnBothEnds);\n+    /*\n+     * PIRE0_EL1 and PIR_EL1 were erroneously unconditionnally exposed\n+     * before linux v6.13. See commit a68cddbe47ef (\"KVM: arm64: Hide\n+     * S1PIE registers from userspace when disabled for guests\")\n+     */\n+    arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 2),\n+                                     0, 0, ToleranceNotOnBothEnds);\n+    arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3),\n+                                     0, 0, ToleranceNotOnBothEnds);\n+}\n+#endif\n+\n static void aarch64_host_initfn(Object *obj)\n {\n     ARMCPU *cpu = ARM_CPU(obj);\n@@ -822,6 +849,7 @@ static void aarch64_host_initfn(Object *obj)\n #endif\n \n #if defined(CONFIG_KVM)\n+    kvm_arm_set_cpreg_mig_tolerances(cpu);\n     kvm_arm_set_cpu_features_from_host(cpu);\n     aarch64_add_sve_properties(obj);\n #elif defined(CONFIG_HVF)\n",
    "prefixes": [
        "v10",
        "4/7"
    ]
}