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{
    "id": 2225149,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225149/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260420123135.350446-4-ajay.nandam@oss.qualcomm.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260420123135.350446-4-ajay.nandam@oss.qualcomm.com>",
    "date": "2026-04-20T12:31:35",
    "name": "[v2,3/3] pinctrl: qcom: lpass-lpi: Resume clocks for GPIO access",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "feaa4785926133d3a80c8e4b973004a58cdf6ffa",
    "submitter": {
        "id": 93131,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/93131/?format=api",
        "name": "Ajay Kumar Nandam",
        "email": "ajay.nandam@oss.qualcomm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260420123135.350446-4-ajay.nandam@oss.qualcomm.com/mbox/",
    "series": [
        {
            "id": 500603,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/500603/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=500603",
            "date": "2026-04-20T12:31:33",
            "name": "pinctrl: qcom: lpass-lpi: Switch to PM clock framework",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/500603/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2225149/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2225149/checks/",
    "tags": {},
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        ],
        "From": "Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>",
        "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>",
        "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n        linux-kernel@vger.kernel.org, mohammad.rafi.shaik@oss.qualcomm.com,\n        ajay.nandam@oss.qualcomm.com",
        "Subject": "[PATCH v2 3/3] pinctrl: qcom: lpass-lpi: Resume clocks for GPIO\n access",
        "Date": "Mon, 20 Apr 2026 18:01:35 +0530",
        "Message-Id": "<20260420123135.350446-4-ajay.nandam@oss.qualcomm.com>",
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        "References": "<20260420123135.350446-1-ajay.nandam@oss.qualcomm.com>",
        "Precedence": "bulk",
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    },
    "content": "Ensure the LPI pinctrl device clocks are runtime resumed\nbefore accessing GPIO registers and autosuspended after\nthe access completes.\n\nGuard GPIO register read and write helpers with synchronous\nruntime PM calls so the device is active during MMIO\noperations.\n\nSigned-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 26 ++++++++++++++++++------\n 1 file changed, 20 insertions(+), 6 deletions(-)",
    "diff": "diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\nindex 2b0956ff2ae0..75ae21478fa4 100644\n--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\n+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c\n@@ -38,32 +38,46 @@ struct lpi_pinctrl {\n \tconst struct lpi_pinctrl_variant_data *data;\n };\n \n-static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,\n+static u32 lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,\n \t\t\t unsigned int addr)\n {\n-\tu32 pin_offset;\n+\tu32 pin_offset, val;\n+\tint ret;\n \n \tif (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)\n \t\tpin_offset = state->data->groups[pin].pin_offset;\n \telse\n \t\tpin_offset = LPI_TLMM_REG_OFFSET * pin;\n \n-\treturn ioread32(state->tlmm_base + pin_offset + addr);\n+\tret = pm_runtime_resume_and_get(state->dev);\n+\tif (ret < 0)\n+\t\treturn 0;\n+\n+\tval = ioread32(state->tlmm_base + pin_offset + addr);\n+\tpm_runtime_put_autosuspend(state->dev);\n+\n+\treturn val;\n }\n \n-static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,\n-\t\t\t  unsigned int addr, unsigned int val)\n+static void lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,\n+\t\t\t   unsigned int addr, unsigned int val)\n {\n \tu32 pin_offset;\n+\tint ret;\n \n \tif (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET)\n \t\tpin_offset = state->data->groups[pin].pin_offset;\n \telse\n \t\tpin_offset = LPI_TLMM_REG_OFFSET * pin;\n \n+\tret = pm_runtime_resume_and_get(state->dev);\n+\tif (ret < 0)\n+\t\treturn;\n+\n \tiowrite32(val, state->tlmm_base + pin_offset + addr);\n+\tpm_runtime_put_autosuspend(state->dev);\n \n-\treturn 0;\n+\treturn;\n }\n \n static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {\n",
    "prefixes": [
        "v2",
        "3/3"
    ]
}