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{
    "id": 2225105,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225105/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-10-biju.das.jz@bp.renesas.com/",
    "project": {
        "id": 38,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api",
        "name": "Linux PWM development",
        "link_name": "linux-pwm",
        "list_id": "linux-pwm.vger.kernel.org",
        "list_email": "linux-pwm@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260420104332.153640-10-biju.das.jz@bp.renesas.com>",
    "date": "2026-04-20T10:43:26",
    "name": "[v5,9/9] pwm: rzg2l-gpt: Add RZ/G3E support",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "18b3b628da16da8536e679d41e49eae7b87d3f86",
    "submitter": {
        "id": 87968,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/87968/?format=api",
        "name": "Biju",
        "email": "biju.das.au@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-10-biju.das.jz@bp.renesas.com/mbox/",
    "series": [
        {
            "id": 500593,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/500593/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593",
            "date": "2026-04-20T10:43:17",
            "name": "Add Renesas RZ/G3E GPT support",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/500593/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2225105/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2225105/checks/",
    "tags": {},
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        "From": "Biju <biju.das.au@gmail.com>",
        "X-Google-Original-From": "Biju <biju.das.jz@bp.renesas.com>",
        "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Magnus Damm <magnus.damm@gmail.com>",
        "Cc": "Biju Das <biju.das.jz@bp.renesas.com>,\n\tlinux-pwm@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tPrabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,\n\tBiju Das <biju.das.au@gmail.com>,\n\tTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>",
        "Subject": "[PATCH v5 9/9] pwm: rzg2l-gpt: Add RZ/G3E support",
        "Date": "Mon, 20 Apr 2026 11:43:26 +0100",
        "Message-ID": "<20260420104332.153640-10-biju.das.jz@bp.renesas.com>",
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        "References": "<20260420104332.153640-1-biju.das.jz@bp.renesas.com>",
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    },
    "content": "From: Biju Das <biju.das.jz@bp.renesas.com>\n\nAdd RZ/G3E GPT support. It has multiple clocks and resets compared to\nRZ/G2L. Also prescale field width and factor for calculating prescale\nare different.\n\nReviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv4->v5:\n * No change.\nv3->v4:\n * Added RZG3E_GTCR_TPCS bit definition for RZ/G3E and added to\n   rzg3e_data.\nv2->v3:\n * No change.\nv1->v2:\n * Added link to hardware manual\n * Updated limitation section\n * Collected tag \n---\n drivers/pwm/pwm-rzg2l-gpt.c | 47 +++++++++++++++++++++++++++++++++++--\n 1 file changed, 45 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c\nindex de68c02b2d50..8cb3e67f4fdb 100644\n--- a/drivers/pwm/pwm-rzg2l-gpt.c\n+++ b/drivers/pwm/pwm-rzg2l-gpt.c\n@@ -6,15 +6,21 @@\n  *\n  * Hardware manual for this IP can be found here\n  * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en\n+ * https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardware\n  *\n  * Limitations:\n  * - Counter must be stopped before modifying Mode and Prescaler.\n  * - When PWM is disabled, the output is driven to inactive.\n  * - While the hardware supports both polarities, the driver (for now)\n  *   only handles normal polarity.\n- * - General PWM Timer (GPT) has 8 HW channels for PWM operations and\n- *   each HW channel have 2 IOs.\n+ * - For RZ/G2L, the General PWM Timer (GPT) has 8 HW channels for PWM\n+     operations and each HW channel have 2 IOs (GTIOCn{A, B}).\n  * - Each IO is modelled as an independent PWM channel.\n+ * - For RZ/G3E, the General PWM Timer (GPT) has 16 HW channels for PWM\n+     operations (GPT0: 8 channels, GPT1: 8 Channels) and each HW channel\n+     have 4 IOs (GTIOCn{A,AN,B,BN}). The 2 extra IOs GTIOCnAN and GTIOCnBN\n+     in RZ/G3E are anti-phase signals of GTIOCnA and GTIOCnB. The\n+     anti-phase signals of RZ/G3E are not modelled as PWM channel.\n  * - When both channels are used, disabling the channel on one stops the\n  *   other.\n  * - When both channels are used, the period of both IOs in the HW channel\n@@ -48,6 +54,7 @@\n #define RZG2L_GTCR_CST\t\tBIT(0)\n #define RZG2L_GTCR_MD\t\tGENMASK(18, 16)\n #define RZG2L_GTCR_TPCS\t\tGENMASK(26, 24)\n+#define RZG3E_GTCR_TPCS\t\tGENMASK(26, 23)\n \n #define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE\tFIELD_PREP(RZG2L_GTCR_MD, 0)\n \n@@ -160,6 +167,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)\n \treturn prescale;\n }\n \n+static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks)\n+{\n+\tu32 prescaled_period_ticks;\n+\tu8 prescale;\n+\n+\tprescaled_period_ticks = period_ticks >> 32;\n+\tif (prescaled_period_ticks >= 64 && prescaled_period_ticks < 256) {\n+\t\tprescale = 6;\n+\t} else if (prescaled_period_ticks >= 256 && prescaled_period_ticks < 1024) {\n+\t\tprescale = 8;\n+\t} else if (prescaled_period_ticks >= 1024) {\n+\t\tprescale = 10;\n+\t} else {\n+\t\tprescale = fls(prescaled_period_ticks);\n+\t\tif (prescale > 1)\n+\t\t\tprescale -= 1;\n+\t}\n+\n+\treturn prescale;\n+}\n+\n static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)\n {\n \tstruct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);\n@@ -545,6 +573,14 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)\n \tif (IS_ERR(rstc))\n \t\treturn dev_err_probe(dev, PTR_ERR(rstc), \"Cannot deassert reset control\\n\");\n \n+\trstc = devm_reset_control_get_optional_exclusive_deasserted(dev, \"rst_s\");\n+\tif (IS_ERR(rstc))\n+\t\treturn dev_err_probe(dev, PTR_ERR(rstc), \"Cannot deassert rst_s reset\\n\");\n+\n+\tclk = devm_clk_get_optional_enabled(dev, \"bus\");\n+\tif (IS_ERR(clk))\n+\t\treturn dev_err_probe(dev, PTR_ERR(clk), \"Cannot get bus clock\\n\");\n+\n \tclk = devm_clk_get_enabled(dev, NULL);\n \tif (IS_ERR(clk))\n \t\treturn dev_err_probe(dev, PTR_ERR(clk), \"Cannot get clock\\n\");\n@@ -587,6 +623,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)\n \treturn 0;\n }\n \n+static const struct rzg2l_gpt_info rzg3e_data = {\n+\t.calculate_prescale = rzg3e_gpt_calculate_prescale,\n+\t.gtcr_tpcs = RZG3E_GTCR_TPCS,\n+\t.prescale_mult = 1,\n+};\n+\n static const struct rzg2l_gpt_info rzg2l_data = {\n \t.calculate_prescale = rzg2l_gpt_calculate_prescale,\n \t.gtcr_tpcs = RZG2L_GTCR_TPCS,\n@@ -594,6 +636,7 @@ static const struct rzg2l_gpt_info rzg2l_data = {\n };\n \n static const struct of_device_id rzg2l_gpt_of_table[] = {\n+\t{ .compatible = \"renesas,r9a09g047-gpt\", .data = &rzg3e_data },\n \t{ .compatible = \"renesas,rzg2l-gpt\", .data = &rzg2l_data },\n \t{ /* Sentinel */ }\n };\n",
    "prefixes": [
        "v5",
        "9/9"
    ]
}