Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2225081/?format=api
{ "id": 2225081, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225081/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-9-biju.das.jz@bp.renesas.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260420104332.153640-9-biju.das.jz@bp.renesas.com>", "date": "2026-04-20T10:43:25", "name": "[v5,8/9] dt-bindings: pwm: Document RZ/G3E GPT support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6f898badc6487268160d8df77f51040607356ee0", "submitter": { "id": 87968, "url": "http://patchwork.ozlabs.org/api/1.1/people/87968/?format=api", "name": "Biju", "email": "biju.das.au@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-9-biju.das.jz@bp.renesas.com/mbox/", "series": [ { "id": 500593, "url": "http://patchwork.ozlabs.org/api/1.1/series/500593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593", "date": "2026-04-20T10:43:17", "name": "Add Renesas RZ/G3E GPT support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225081/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225081/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pwm+bounces-8642-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=NT5IKr4s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8642-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"NT5IKr4s\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.53", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzhy257lKz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 20 Apr 2026 20:47:06 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 1EC703022E37\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 20 Apr 2026 10:44:31 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3646539E193;\n\tMon, 20 Apr 2026 10:43:47 +0000 (UTC)", "from mail-wm1-f53.google.com (mail-wm1-f53.google.com\n [209.85.128.53])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 82D1E39D6FF\n\tfor <linux-pwm@vger.kernel.org>; Mon, 20 Apr 2026 10:43:44 +0000 (UTC)", "by mail-wm1-f53.google.com with SMTP id\n 5b1f17b1804b1-483487335c2so28145295e9.2\n for <linux-pwm@vger.kernel.org>; Mon, 20 Apr 2026 03:43:44 -0700 (PDT)", "from localhost.localdomain\n ([2a00:23c4:a758:8a01:5f3e:f914:6f8c:72c3])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43fe4c221cdsm28038301f8f.0.2026.04.20.03.43.41\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 20 Apr 2026 03:43:42 -0700 (PDT)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776681827; cv=none;\n b=W2Zk/E3EtyNx1eCISYHBBpaMfNWWUpGppVpRUrOlvlCn5uGkgsNHIutLrdxGJw5qoL1SxIqNgIQLcvNhhKylt04Tht/6+PUqd2c5zRg+HfgNz5FOj/GDykbJcDZnRG/etUwpkz86W/RdVRJSDASpW0F80/9phTcLI9ByaiCdy3o=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776681827; c=relaxed/simple;\n\tbh=aSc61WI2GCRv4io4Xwk6XQ589ru7d382pkZgvtVmxZo=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=I4SBeojNdCg2KL1dIE5bEV5oXCOnPVzHDBYe046MbzFcXcCEJYNy0d8JIhbnP4InHFknSyX3e7092fKnJ9fOswiiAzBJ6gfful7waaobSpt/4vFyQtNZ5/+rZoKG3ygczJsgW5l8JG+1HH5Gd9BZsO2txzzg1r6yfBYifelmh8o=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com;\n spf=pass smtp.mailfrom=gmail.com;\n dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=NT5IKr4s; arc=none smtp.client-ip=209.85.128.53", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1776681823; x=1777286623;\n darn=vger.kernel.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=6qejXMPJoK1szlmp+NPBWtIuGPTckrdO8Ea5i79s798=;\n b=NT5IKr4sPA7pjuzOgjbl02KUzdzozZalJpPmS5I7FsMjLuUrjuODcEiCeGrw/ryu2J\n y3mg3cxPMYkKJ67JeG5AvMMrobOVjXUrnky6eQWXQJficckerkTrkoeKux+qmG7mvr+h\n yvWQTUFhG5alFj5VKFrwLfpQLrAPnfP+HhXQENsXCRvbw0cY8x0pLzndByLX2LLk1BmP\n gZzGRyU+BJp5+7gtA57AFaa46ttkUgRISbqpbUcTkmcfBzrcg/1PF2e/auAUVCE1vp/0\n CSDfxt+5mkvnvTMURU/RdRK35rJQy8WUOTvbg/UaeKpYdp83p9BqBM8H16iA8wFKCqeq\n OhdQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1776681823; x=1777286623;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=6qejXMPJoK1szlmp+NPBWtIuGPTckrdO8Ea5i79s798=;\n b=K66JbXuB8V1Q8wmS2p2zd6KLVKNgbAgbLUB7w+JpwfhOJXNoQozCIKKYq3RtgifZqu\n UQ7tmsICdSJbMRmY+JzZij8XkqQiWXYT4UleYXadaiYrYoVHKqZ6gKZecdrhJN5bH5Jh\n gXpH6d8pF2Zshgqz89MxxHJ/0o8wgrh/kc4hJGTK3lWYhJg09XdfAQrwIWAqmmf1VDCk\n C5Aj7Qw/4RIT4ZpCkCa48OV8DbVx/F6cfEShObEOkV4d57OCBDf3xWdtUWqU2Mx+o6E7\n 7xypeonHbK6CY20cD119IgPeSKXDkG/elVQjaBJ93IAf3arjEw+tG4iOhSMoHsQqf9o/\n racQ==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ85YslzwX1xmJrcAKQAQO6QOVLDULsbYJORye+1i5UYHehZgMIeheBZMtPG3+qqsXBaSJId3I93pR8=@vger.kernel.org", "X-Gm-Message-State": "AOJu0Yx5MRie9DDqjDmiIFRpiPX/gyqUIhewhfiNeGe9aX84ARFRZau0\n\tHdCDemaMPYDrarG3OdesHCLU3Hvy7RIqtT1i3B9JCCTAoSrmyYp3rZPA", "X-Gm-Gg": "AeBDieuBJMuMCw3f4EVImst8j9FbntWOghEJjpArowN8FR0R+Kri0TwqTBPvpgeXVbI\n\tfwuEkpw5blDmobx4LsIKRtVcXEIyztd3FkDEGaY4BIShP6Gu5VjLdWC2lphGEESIM6cV19lSLyv\n\tHZ8+0z4iXaHidxsqfU9pUTZF0IDh5Q5Ht1vKr6qwATgIK/5BpZmQq5e9xGoBUu78/jXm+a4HVg4\n\tYvlZwnnhN1PeLbJKr3jmOMYvPdixZc2e2dCy8+JsMveNr5swbzp8quxWJ2FpIWOryg85qZEzmmc\n\tKjXqqLxK+44QQP3q81P779Zr5mOwJevyV9V0yYgUV5e51cDynqz7kFpq9DQz9imYM1NmIa920x6\n\tr77o8vJxfMCGxQWJruW8g1eMk+SC7BqA0pHRn7WEU24PU/mJ3J+p2HU8NA4e7EF12NCmDnpP8+w\n\twb4jkJzMIehl5/4CSwvO8VmuYzNyG5Ng8XKUjjvJMpvrXSJ8XxAj9DxrKVNO4=", "X-Received": "by 2002:a05:600c:34c3:b0:485:41c4:e2e4 with SMTP id\n 5b1f17b1804b1-488fb792dd0mr184333935e9.23.1776681822758;\n Mon, 20 Apr 2026 03:43:42 -0700 (PDT)", "From": "Biju <biju.das.au@gmail.com>", "X-Google-Original-From": "Biju <biju.das.jz@bp.renesas.com>", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Magnus Damm <magnus.damm@gmail.com>", "Cc": "Biju Das <biju.das.jz@bp.renesas.com>,\n\tlinux-pwm@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tPrabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,\n\tBiju Das <biju.das.au@gmail.com>", "Subject": "[PATCH v5 8/9] dt-bindings: pwm: Document RZ/G3E GPT support", "Date": "Mon, 20 Apr 2026 11:43:25 +0100", "Message-ID": "<20260420104332.153640-9-biju.das.jz@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260420104332.153640-1-biju.das.jz@bp.renesas.com>", "References": "<20260420104332.153640-1-biju.das.jz@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Biju Das <biju.das.jz@bp.renesas.com>\n\nDocument support for the GPT found on the Renesas RZ/G3E (R9A09G047)\nSoC.\n\nThe GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel\nand GPT1: 8channels). The hardware supports simultaneous control of\nall channels. PWM waveforms can be generated by controlling the\nup-counter, downcounter, or up- and down-counter.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv4->v5:\n * No change.\nv3->v4:\n * No change.\nv2->v3:\n * Added Rb tag from Rob.\nv1->v2:\n * Created separate document for RZ/G3E GPT.\n * Updated commit header and description.\n---\n .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++\n 1 file changed, 323 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml\nnew file mode 100644\nindex 000000000000..cb4ffab5f47f\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml\n@@ -0,0 +1,323 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pwm/renesas,rzg3e-gpt.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Renesas RZ/G3E General PWM Timer (GPT)\n+\n+maintainers:\n+ - Biju Das <biju.das.jz@bp.renesas.com>\n+\n+description: |\n+ RZ/G3E General PWM Timer (GPT) composed of 16 channels with 32-bit\n+ timer. It supports the following functions\n+ * 32 bits x 16 channels.\n+ * Up-counting or down-counting (saw waves) or up/down-counting\n+ (triangle waves) for each counter.\n+ * Clock sources independently selectable for each channel.\n+ * Four I/O pins per channel.\n+ * Two output compare/input capture registers per channel.\n+ * For the two output compare/input capture registers of each channel,\n+ four registers are provided as buffer registers and are capable of\n+ operating as comparison registers when buffering is not in use.\n+ * In output compare operation, buffer switching can be at crests or\n+ troughs, enabling the generation of laterally asymmetric PWM waveforms.\n+ * Registers for setting up frame cycles in each channel (with capability\n+ for generating interrupts at overflow or underflow)\n+ * Generation of dead times in PWM operation.\n+ * Synchronous starting, stopping and clearing counters for arbitrary\n+ channels.\n+ * Count start, count stop, count clear, up-count, down-count, or input\n+ capture operation in response to a maximum of 8 ELC events.\n+ * Count start, count stop, count clear, up-count, down-count, or input\n+ capture operation in response to the status of two input pins.\n+ * Starting, clearing, stopping and up/down counters in response to a\n+ maximum of four external triggers.\n+ * Output pin disable function by detected short-circuits between output\n+ pins.\n+ * A/D converter start triggers can be generated.\n+ * Compare match A to F event and overflow/underflow event can be output\n+ to the ELC.\n+ * Enables the noise filter for input capture.\n+ * Logical operation between the channel output.\n+\n+properties:\n+ compatible:\n+ items:\n+ - const: renesas,r9a09g047-gpt # RZ/G3E\n+\n+ reg:\n+ maxItems: 1\n+\n+ '#pwm-cells':\n+ const: 3\n+\n+ interrupts:\n+ items:\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.0\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.0\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.0\n+ - description: A and B both high interrupt for channel GPT{0,1}.0\n+ - description: A and B both low interrupt for channel GPT{0,1}.0\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.1\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.1\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.1\n+ - description: A and B both high interrupt for channel GPT{0,1}.1\n+ - description: A and B both low interrupt for channel GPT{0,1}.1\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.2\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.2\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.2\n+ - description: A and B both high interrupt for channel GPT{0,1}.2\n+ - description: A and B both low interrupt for channel GPT{0,1}.2\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.3\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.3\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.3\n+ - description: A and B both high interrupt for channel GPT{0,1}.3\n+ - description: A and B both low interrupt for channel GPT{0,1}.3\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.4\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.4\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.4\n+ - description: A and B both high interrupt for channel GPT{0,1}.4\n+ - description: A and B both low interrupt for channel GPT{0,1}.4\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.5\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.5\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.5\n+ - description: A and B both high interrupt for channel GPT{0,1}.5\n+ - description: A and B both low interrupt for channel GPT{0,1}.5\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.6\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.6\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.6\n+ - description: A and B both high interrupt for channel GPT{0,1}.6\n+ - description: A and B both low interrupt for channel GPT{0,1}.6\n+ - description: Input capture/compare match of the GTCCRA for channel GPT{0,1}.7\n+ - description: Input capture/compare match of the GTCCRB for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRC for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRD for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRE for channel GPT{0,1}.7\n+ - description: Compare match with the GTCCRF for channel GPT{0,1}.7\n+ - description: A and B both high interrupt for channel GPT{0,1}.7\n+ - description: A and B both low interrupt for channel GPT{0,1}.7\n+\n+ interrupt-names:\n+ items:\n+ - const: gtcia0\n+ - const: gtcib0\n+ - const: gtcic0\n+ - const: gtcid0\n+ - const: gtcie0\n+ - const: gtcif0\n+ - const: gtcih0\n+ - const: gtcil0\n+ - const: gtcia1\n+ - const: gtcib1\n+ - const: gtcic1\n+ - const: gtcid1\n+ - const: gtcie1\n+ - const: gtcif1\n+ - const: gtcih1\n+ - const: gtcil1\n+ - const: gtcia2\n+ - const: gtcib2\n+ - const: gtcic2\n+ - const: gtcid2\n+ - const: gtcie2\n+ - const: gtcif2\n+ - const: gtcih2\n+ - const: gtcil2\n+ - const: gtcia3\n+ - const: gtcib3\n+ - const: gtcic3\n+ - const: gtcid3\n+ - const: gtcie3\n+ - const: gtcif3\n+ - const: gtcih3\n+ - const: gtcil3\n+ - const: gtcia4\n+ - const: gtcib4\n+ - const: gtcic4\n+ - const: gtcid4\n+ - const: gtcie4\n+ - const: gtcif4\n+ - const: gtcih4\n+ - const: gtcil4\n+ - const: gtcia5\n+ - const: gtcib5\n+ - const: gtcic5\n+ - const: gtcid5\n+ - const: gtcie5\n+ - const: gtcif5\n+ - const: gtcih5\n+ - const: gtcil5\n+ - const: gtcia6\n+ - const: gtcib6\n+ - const: gtcic6\n+ - const: gtcid6\n+ - const: gtcie6\n+ - const: gtcif6\n+ - const: gtcih6\n+ - const: gtcil6\n+ - const: gtcia7\n+ - const: gtcib7\n+ - const: gtcic7\n+ - const: gtcid7\n+ - const: gtcie7\n+ - const: gtcif7\n+ - const: gtcih7\n+ - const: gtcil7\n+\n+ clocks:\n+ items:\n+ - description: Core clock (PCLKD)\n+ - description: Bus clock (PCLKA)\n+\n+ clock-names:\n+ items:\n+ - const: core\n+ - const: bus\n+\n+ power-domains:\n+ maxItems: 1\n+\n+ resets:\n+ items:\n+ - description: Reset for bus clock (PCLKA/PCLKD)\n+ - description: Reset for core clock (PCLKD)\n+\n+ reset-names:\n+ items:\n+ - const: rst_p\n+ - const: rst_s\n+\n+required:\n+ - compatible\n+ - reg\n+ - interrupts\n+ - interrupt-names\n+ - clocks\n+ - clock-names\n+ - power-domains\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: pwm.yaml#\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ pwm@13010000 {\n+ compatible = \"renesas,r9a09g047-gpt\";\n+ reg = <0x13010000 0x10000>;\n+ interrupts = <GIC_SPI 538 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 554 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 562 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 570 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 586 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 594 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 539 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 555 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 563 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 571 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 579 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 540 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 548 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 556 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 572 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 580 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 588 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 541 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 549 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 557 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 573 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 581 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 589 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 597 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 542 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 550 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 558 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 566 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 582 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 590 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 598 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 543 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 551 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 559 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 567 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 575 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 544 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 552 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 560 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 568 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 584 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 553 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 561 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 569 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 577 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 593 IRQ_TYPE_EDGE_RISING>,\n+ <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>;\n+ interrupt-names = \"gtcia0\", \"gtcib0\", \"gtcic0\", \"gtcid0\",\n+ \"gtcie0\", \"gtcif0\", \"gtcih0\", \"gtcil0\",\n+ \"gtcia1\", \"gtcib1\", \"gtcic1\", \"gtcid1\",\n+ \"gtcie1\", \"gtcif1\", \"gtcih1\", \"gtcil1\",\n+ \"gtcia2\", \"gtcib2\", \"gtcic2\", \"gtcid2\",\n+ \"gtcie2\", \"gtcif2\", \"gtcih2\", \"gtcil2\",\n+ \"gtcia3\", \"gtcib3\", \"gtcic3\", \"gtcid3\",\n+ \"gtcie3\", \"gtcif3\", \"gtcih3\", \"gtcil3\",\n+ \"gtcia4\", \"gtcib4\", \"gtcic4\", \"gtcid4\",\n+ \"gtcie4\", \"gtcif4\", \"gtcih4\", \"gtcil4\",\n+ \"gtcia5\", \"gtcib5\", \"gtcic5\", \"gtcid5\",\n+ \"gtcie5\", \"gtcif5\", \"gtcih5\", \"gtcil5\",\n+ \"gtcia6\", \"gtcib6\", \"gtcic6\", \"gtcid6\",\n+ \"gtcie6\", \"gtcif6\", \"gtcih6\", \"gtcil6\",\n+ \"gtcia7\", \"gtcib7\", \"gtcic7\", \"gtcid7\",\n+ \"gtcie7\", \"gtcif7\", \"gtcih7\", \"gtcil7\";\n+ clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;\n+ clock-names = \"core\", \"bus\";\n+ power-domains = <&cpg>;\n+ resets = <&cpg 0x59>, <&cpg 0x5a>;\n+ reset-names = \"rst_p\", \"rst_s\";\n+ #pwm-cells = <3>;\n+ };\n", "prefixes": [ "v5", "8/9" ] }