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GET /api/1.1/patches/2225071/?format=api
{ "id": 2225071, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225071/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420104248.86702-14-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260420104248.86702-14-mohamed@unpredictable.fr>", "date": "2026-04-20T10:42:23", "name": "[v2,13/38] whpx: i386: interrupt priority support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a8928d6db7320caa8f26526718c6a0a6a64b31e1", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/1.1/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260420104248.86702-14-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 500592, "url": "http://patchwork.ozlabs.org/api/1.1/series/500592/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500592", "date": "2026-04-20T10:42:10", "name": "WHPX x86 updates for QEMU 11.1", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500592/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225071/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225071/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=JgWCaSVE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fzhwm4xlkz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 20 Apr 2026 20:46:00 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wEm6Q-00079X-H8; Mon, 20 Apr 2026 06:43:42 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wEm6E-0006xj-QG\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 06:43:31 -0400", "from p-west3-cluster5-host11-snip4-5.eps.apple.com ([57.103.72.108]\n helo=outbound.ms.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wEm6C-0000ao-SF\n for qemu-devel@nongnu.org; Mon, 20 Apr 2026 06:43:30 -0400", "from outbound.ms.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-west-3a-100-percent-1 (Postfix) with ESMTPS id\n 7177918000BF; Mon, 20 Apr 2026 10:43:26 +0000 (UTC)", "from localhost.localdomain (unknown [17.57.154.37])\n by p00-icloudmta-asmtp-us-west-3a-100-percent-1 (Postfix) with ESMTPSA id\n D3B251800453; Mon, 20 Apr 2026 10:43:23 +0000 (UTC)" ], "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1776681807; x=1779273807;\n bh=3V2AbGdIbRhzhb8qduzZPT33vmWH+5zkQKA9bxE3tcA=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=JgWCaSVEugXlN49xCAIBBThh2GbMf0C2o4t3BXF6rIFK64sazePCyhM+yMZQYRsW09f2xUM/ILHbd1LM9UvAE/LThGSvj83cEDL9WuSZikWtgFzAbQHpsUo1CEoewxdtIN5WCHSZZVFkKGPOSI9HjXIhnrpTGCZIW3joZBYUun2BxTUqAV7otF+adMaGE8ZXDFmD88s4kZAxOEEWWkhxdT2P5iMDAwkuvXC5E13TxFiurNScj5Zj/OTDKjUbiKW042WX6hdXVuA/+moUdRIuiQ4brl1O9nvE0zlgWnbjkczvkVWRjmNdY7ZpsJnNpnGP4QYO7SWdnVOGHk80zBCqtQ==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org, Mohamed Mediouni <mohamed@unpredictable.fr>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Phil Dennis-Jordan <phil@philjordan.eu>,\n Roman Bolshakov <rbolshakov@ddn.com>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Pedro Barbuda <pbarbuda@microsoft.com>, Wei Liu <wei.liu@kernel.org>,\n \"Michael S. Tsirkin\" <mst@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>, Zhao Liu <zhao1.liu@intel.com>", "Subject": "[PATCH v2 13/38] whpx: i386: interrupt priority support", "Date": "Mon, 20 Apr 2026 12:42:23 +0200", "Message-ID": "<20260420104248.86702-14-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260420104248.86702-1-mohamed@unpredictable.fr>", "References": "<20260420104248.86702-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "-SxLM4dJTJev-AiykB4STG2w6MD6DZ2D", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIwMDEwNCBTYWx0ZWRfX3XW3xQb9Sawf\n Tg+P5z5Rk9A7r1oWnc+UMoM6rGN9bQ8azLXr87OKJMuJa1mnJBqOW/euElhCBIHorP77aK9leJ/\n qf/ubyItpyQfrKpi8sKTF8l0U+3k8Hmdcm83d/PsQIQPVH99rF7XgqOC8rZkva1OMSm7zJ+1Dnl\n BndrJ6h7QV4ckod3IGuLduBDuNsxjsKMehDrOPCJX0DCTLgrY8N/8cy09/C6fEcbZn2uP0RHI48\n vDqn2W0yv39OGfq4xKj/Hb3bp83u1GZViNsvCFQTQaYibGGL+vsiaXe2J6AWFRhKqwtcGfyVk1f\n qyFuhohJ037yOCni4WVpllI13p7QiYkzJcDC8KNIW3ZLK7ODvA0y5xhB0jZenM=", "X-Proofpoint-ORIG-GUID": "-SxLM4dJTJev-AiykB4STG2w6MD6DZ2D", "X-Authority-Info-Out": "v=2.4 cv=ce7fb3DM c=1 sm=1 tr=0 ts=69e6034f\n cx=c_apl:c_pps:t_out a=qkKslKyYc0ctBTeLUVfTFg==:117 a=A5OVakUREuEA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=NuKELtICf0aykZwt-QIA:9", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-20_02,2026-04-17_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0 spamscore=0\n lowpriorityscore=0 malwarescore=0 mlxlogscore=687 bulkscore=0 adultscore=0\n mlxscore=0 suspectscore=0 clxscore=1030 phishscore=0 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604200104", "Received-SPF": "pass client-ip=57.103.72.108;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement APIC IRR interrupt priorities.\n\nEven with kernel-irqchip=off, Hyper-V is aware of interrupt priorities\nand implements CR8/TPR, with the InterruptPriority field being followed.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n target/i386/whpx/whpx-all.c | 24 ++++++++++++++++++++----\n 1 file changed, 20 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex d38b83d274..930731e4bf 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -1588,6 +1588,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n UINT32 reg_count = 0;\n WHV_REGISTER_VALUE reg_values[3];\n WHV_REGISTER_NAME reg_names[3];\n+ int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);\n \n memset(&new_int, 0, sizeof(new_int));\n memset(reg_values, 0, sizeof(reg_values));\n@@ -1623,10 +1624,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n }\n \n+ if (irr == -1) {\n+ if (isa_pic != NULL && pic_get_output(isa_pic)) {\n+ /* In case it's a PIC interrupt */\n+ irr = 0;\n+ } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n+ abort();\n+ }\n+ }\n+\n /* Get pending hard interruption or replay one that was overwritten */\n if (!whpx_irqchip_in_kernel()) {\n if (!vcpu->interruption_pending &&\n- vcpu->interruptable && (env->eflags & IF_MASK)) {\n+ vcpu->interruptable && (env->eflags & IF_MASK)\n+ && (vcpu->tpr < irr || irr == 0)) {\n assert(!new_int.InterruptionPending);\n if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);\n@@ -1683,13 +1694,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Update the state of the interrupt delivery notification */\n- if (!vcpu->window_registered &&\n+ if ((!vcpu->window_registered ||\n+ (vcpu->window_priority < irr && vcpu->window_priority != 0) ||\n+ (irr == 0 && vcpu->window_priority != 0)) &&\n cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n reg_values[reg_count].DeliverabilityNotifications =\n (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {\n- .InterruptNotification = 1\n+ .InterruptNotification = 1,\n+ .InterruptPriority = irr >> 4\n };\n vcpu->window_registered = 1;\n+ vcpu->window_priority = irr;\n reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;\n reg_count += 1;\n }\n@@ -1703,7 +1718,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n reg_names, reg_count, reg_values);\n if (FAILED(hr)) {\n error_report(\"WHPX: Failed to set interrupt state registers,\"\n- \" hr=%08lx\", hr);\n+ \" hr=%08lx, InterruptPriority=%i\", hr, irr >> 4);\n }\n }\n }\n@@ -1919,6 +1934,7 @@ int whpx_vcpu_run(CPUState *cpu)\n case WHvRunVpExitReasonX64InterruptWindow:\n vcpu->ready_for_pic_interrupt = 1;\n vcpu->window_registered = 0;\n+ vcpu->window_priority = 0;\n ret = 0;\n break;\n \n", "prefixes": [ "v2", "13/38" ] }