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GET /api/1.1/patches/2225063/?format=api
{ "id": 2225063, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2225063/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-6-biju.das.jz@bp.renesas.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260420104332.153640-6-biju.das.jz@bp.renesas.com>", "date": "2026-04-20T10:43:22", "name": "[v5,5/9] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7f12e455dbea395435e5f35cc4aa6e66dc0d5db8", "submitter": { "id": 87968, "url": "http://patchwork.ozlabs.org/api/1.1/people/87968/?format=api", "name": "Biju", "email": "biju.das.au@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/patch/20260420104332.153640-6-biju.das.jz@bp.renesas.com/mbox/", "series": [ { "id": 500593, "url": "http://patchwork.ozlabs.org/api/1.1/series/500593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593", "date": "2026-04-20T10:43:17", "name": "Add Renesas RZ/G3E GPT support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225063/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225063/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pwm+bounces-8639-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ApMkzdtg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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This is needed because the RZ/G3E GPT has a 4-bit\nprescaler field versus the 3-bit field on RZ/G2L.\n\nReviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv4->v5:\n * Updated commit description.\nv3->v4:\n * Dropped field_{get,prep} as mainline now support it.\n * Updated commit description.\n * Retained RZG2L_GTCR_TPCS bit definitons\n * Replaced gtcr_tpcs_mask->gtcr_tpcs\nv2->v3:\n * No change.\nv1->v2:\n * Collected tag.\n---\n drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++++----\n 1 file changed, 15 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c\nindex 9e7a897a0b4d..af594c1ce536 100644\n--- a/drivers/pwm/pwm-rzg2l-gpt.c\n+++ b/drivers/pwm/pwm-rzg2l-gpt.c\n@@ -90,9 +90,14 @@\n #define RZG2L_MAX_POEG_GROUPS\t4\n #define RZG2L_LAST_POEG_GROUP\t3\n \n+struct rzg2l_gpt_info {\n+\tu32 gtcr_tpcs;\n+};\n+\n struct rzg2l_gpt_chip {\n \tvoid __iomem *mmio;\n \tstruct mutex lock; /* lock to protect shared channel resources */\n+\tconst struct rzg2l_gpt_info *info;\n \tunsigned long rate_khz;\n \tu32 period_ticks[RZG2L_MAX_HW_CHANNELS];\n \tu32 channel_request_count[RZG2L_MAX_HW_CHANNELS];\n@@ -346,7 +351,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chip,\n \n \tguard(mutex)(&rzg2l_gpt->lock);\n \tif (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) {\n-\t\twfhw->prescale = FIELD_GET(RZG2L_GTCR_TPCS, gtcr);\n+\t\twfhw->prescale = field_get(rzg2l_gpt->info->gtcr_tpcs, gtcr);\n \t\twfhw->gtpr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));\n \t\twfhw->gtccr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));\n \t\tif (wfhw->gtccr > wfhw->gtpr)\n@@ -386,8 +391,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *chip,\n \t\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTING);\n \n \t\t/* Select count clock */\n-\t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,\n-\t\t\t\t FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale));\n+\t\trzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs,\n+\t\t\t\t field_prep(rzg2l_gpt->info->gtcr_tpcs, wfhw->prescale));\n \n \t\t/* Set period */\n \t\trzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr);\n@@ -527,6 +532,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)\n \tif (IS_ERR(rzg2l_gpt->mmio))\n \t\treturn PTR_ERR(rzg2l_gpt->mmio);\n \n+\trzg2l_gpt->info = of_device_get_match_data(dev);\n+\n \trstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);\n \tif (IS_ERR(rstc))\n \t\treturn dev_err_probe(dev, PTR_ERR(rstc), \"Cannot deassert reset control\\n\");\n@@ -573,8 +580,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)\n \treturn 0;\n }\n \n+static const struct rzg2l_gpt_info rzg2l_data = {\n+\t.gtcr_tpcs = RZG2L_GTCR_TPCS,\n+};\n+\n static const struct of_device_id rzg2l_gpt_of_table[] = {\n-\t{ .compatible = \"renesas,rzg2l-gpt\", },\n+\t{ .compatible = \"renesas,rzg2l-gpt\", .data = &rzg2l_data },\n \t{ /* Sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);\n", "prefixes": [ "v5", "5/9" ] }