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GET /api/1.1/patches/2224897/?format=api
{ "id": 2224897, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2224897/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260419130139.15554-9-alexander@mihalicyn.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260419130139.15554-9-alexander@mihalicyn.com>", "date": "2026-04-19T13:01:39", "name": "[v6,8/8] tests/qtest/nvme-test: add migration test with full CQ", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4b700d8e0a5f6110d0458c6a7ee269badedeac8b", "submitter": { "id": 81630, "url": "http://patchwork.ozlabs.org/api/1.1/people/81630/?format=api", "name": "Alexander Mikhalitsyn", "email": "alexander@mihalicyn.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260419130139.15554-9-alexander@mihalicyn.com/mbox/", "series": [ { "id": 500500, "url": "http://patchwork.ozlabs.org/api/1.1/series/500500/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500500", "date": "2026-04-19T13:01:32", "name": "hw/nvme: add basic live migration support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/500500/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224897/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224897/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n secure) header.d=mihalicyn.com header.i=@mihalicyn.com header.a=rsa-sha256\n header.s=mihalicyn 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5b1f17b1804b1-488fb73d525mr115373365e9.5.1776603711438;\n Sun, 19 Apr 2026 06:01:51 -0700 (PDT)", "From": "Alexander Mikhalitsyn <alexander@mihalicyn.com>", "To": "qemu-devel@nongnu.org", "Cc": "Alexander Mikhalitsyn <alexander@mihalicyn.com>,\n Kevin Wolf <kwolf@redhat.com>, qemu-block@nongnu.org,\n Fam Zheng <fam@euphon.net>,\n =?utf-8?q?St=C3=A9phane_Graber?= <stgraber@stgraber.org>, =?utf-8?q?Philipp?=\n\t=?utf-8?q?e_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Stefan Hajnoczi <stefanha@redhat.com>,\n Laurent Vivier <lvivier@redhat.com>, Jesper Devantier <foss@defmacro.it>,\n Klaus Jensen <its@irrelevant.dk>, Fabiano Rosas <farosas@suse.de>,\n Zhao Liu <zhao1.liu@intel.com>, Keith Busch <kbusch@kernel.org>,\n Peter Xu <peterx@redhat.com>, Hanna Reitz <hreitz@redhat.com>,\n Alexander Mikhalitsyn <aleksandr.mikhalitsyn@futurfusion.io>", "Subject": "[PATCH v6 8/8] tests/qtest/nvme-test: add migration test with full CQ", "Date": "Sun, 19 Apr 2026 15:01:39 +0200", "Message-ID": "<20260419130139.15554-9-alexander@mihalicyn.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260419130139.15554-1-alexander@mihalicyn.com>", "References": "<20260419130139.15554-1-alexander@mihalicyn.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=alexander@mihalicyn.com; helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Alexander Mikhalitsyn <aleksandr.mikhalitsyn@futurfusion.io>\n\nAs suggested by Stefan [1], let's add a migration test to cover\nrare scenario when CQ is full of non-processed CQEs and migration\nhappens.\n\nTo run this test:\n$ meson test -C build 'qtest-x86_64/qos-test'\n\nLink: https://lore.kernel.org/qemu-devel/20260408183529.GB319710@fedora/ [1]\nSuggested-by: Stefan Hajnoczi <stefanha@redhat.com>\nSigned-off-by: Alexander Mikhalitsyn <aleksandr.mikhalitsyn@futurfusion.io>\n---\n tests/qtest/nvme-test.c | 393 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 393 insertions(+)", "diff": "diff --git a/tests/qtest/nvme-test.c b/tests/qtest/nvme-test.c\nindex 4aec1651e6e..1ba2fa6943f 100644\n--- a/tests/qtest/nvme-test.c\n+++ b/tests/qtest/nvme-test.c\n@@ -8,9 +8,11 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"qemu/bswap.h\"\n #include \"qemu/module.h\"\n #include \"qemu/units.h\"\n #include \"libqtest.h\"\n+#include \"libqtest-single.h\"\n #include \"libqos/qgraph.h\"\n #include \"libqos/pci.h\"\n #include \"block/nvme.h\"\n@@ -142,6 +144,395 @@ static void nvmetest_pmr_reg_test(void *obj, void *data, QGuestAllocator *alloc)\n qpci_iounmap(pdev, pmr_bar);\n }\n \n+#define PAGE_SIZE 4096\n+\n+typedef struct nvme_ctrl nvme_ctrl;\n+\n+typedef struct nvme_queue {\n+ nvme_ctrl *ctrl;\n+ uint64_t doorbell;\n+ uint32_t size;\n+} nvme_queue;\n+\n+typedef struct nvme_cq {\n+ nvme_queue common;\n+ NvmeCqe *phys_cqe;\n+ uint16_t head;\n+ uint8_t phase;\n+} nvme_cq;\n+\n+typedef struct nvme_sq {\n+ nvme_queue common;\n+ NvmeCmd *phys_sqe;\n+ nvme_cq *cq;\n+ uint16_t head;\n+ uint16_t tail;\n+} nvme_sq;\n+\n+struct nvme_ctrl {\n+ QGuestAllocator *alloc;\n+ QPCIDevice *pdev;\n+ QPCIBar bar;\n+\n+ uint32_t db_stride;\n+\n+ nvme_sq admin_sq;\n+ nvme_cq admin_cq;\n+};\n+\n+static void nvme_init_queue_common(nvme_ctrl *ctrl, nvme_queue *q,\n+ uint16_t db_idx, uint32_t size)\n+{\n+ q->ctrl = ctrl;\n+ q->doorbell = (sizeof(NvmeBar) + db_idx * ctrl->db_stride);\n+ g_test_message(\" q %p db_idx %u doorbell %lx\", q, db_idx, q->doorbell);\n+ q->size = size;\n+}\n+\n+static void nvme_init_sq(nvme_ctrl *ctrl, nvme_sq *sq, uint16_t db_idx,\n+ uint32_t size, nvme_cq *cq)\n+{\n+ nvme_init_queue_common(ctrl, &sq->common, db_idx, size);\n+\n+ sq->phys_sqe = (typeof(sq->phys_sqe))guest_alloc(ctrl->alloc,\n+ PAGE_SIZE);\n+ g_assert(sq->phys_sqe);\n+\n+ g_test_message(\"sq %p db_idx %u sqe %p\", sq, db_idx, sq->phys_sqe);\n+ sq->cq = cq;\n+ sq->head = 0;\n+ sq->tail = 0;\n+}\n+\n+static void nvme_init_cq(nvme_ctrl *ctrl, nvme_cq *cq, uint16_t db_idx,\n+ uint32_t size)\n+{\n+ nvme_init_queue_common(ctrl, &cq->common, db_idx, size);\n+\n+ cq->phys_cqe = (typeof(cq->phys_cqe))guest_alloc(ctrl->alloc,\n+ PAGE_SIZE);\n+ g_assert(cq->phys_cqe);\n+\n+ g_test_message(\"cq %p db_idx %u cqe %p\", cq, db_idx, cq->phys_cqe);\n+ cq->head = 0;\n+ cq->phase = 1;\n+}\n+\n+static int nvme_cqe_pending(nvme_cq *cq)\n+{\n+ uint16_t status = qtest_readw(cq->common.ctrl->pdev->bus->qts,\n+ (uint64_t)&cq->phys_cqe[cq->head].status);\n+ return (le16_to_cpu(status) & 1) == cq->phase;\n+}\n+\n+static int nvme_is_cqe_success(NvmeCqe *cqe)\n+{\n+ return (le16_to_cpu(cqe->status) >> 1) == NVME_SUCCESS;\n+}\n+\n+static NvmeCqe nvme_handle_cqe(nvme_sq *sq)\n+{\n+ nvme_cq *cq = sq->cq;\n+ NvmeCqe *phys_cqe = &cq->phys_cqe[cq->head];\n+ NvmeCqe cqe;\n+ uint16_t cq_next_head;\n+\n+ g_assert(nvme_cqe_pending(cq));\n+\n+ qtest_memread(sq->common.ctrl->pdev->bus->qts, (uint64_t)phys_cqe, &cqe, sizeof(cqe));\n+\n+ cq_next_head = (cq->head + 1) % cq->common.size;\n+ g_test_message(\"cq %p head %u -> %u\", cq, cq->head, cq_next_head);\n+ if (cq_next_head < cq->head) {\n+ cq->phase ^= 1;\n+ }\n+ cq->head = cq_next_head;\n+\n+ if (cqe.sq_head != sq->head) {\n+ sq->head = cqe.sq_head;\n+ g_test_message(\"sq %p head = %u\", sq, sq->head);\n+ }\n+\n+ qpci_io_writel(cq->common.ctrl->pdev, cq->common.ctrl->bar, cq->common.doorbell, cq->head);\n+\n+ return cqe;\n+}\n+\n+static NvmeCqe nvme_wait(nvme_sq *sq)\n+{\n+ int i;\n+ bool ready = false;\n+\n+ for (i = 0; i < 10; i++) {\n+ if (nvme_cqe_pending(sq->cq)) {\n+ ready = true;\n+ break;\n+ }\n+\n+ g_usleep(1000);\n+ }\n+\n+ g_assert(ready);\n+\n+ return nvme_handle_cqe(sq);\n+}\n+\n+static NvmeCmd *nvme_get_next_sqe(nvme_sq *sq, uint8_t opcode, uint16_t cid, void *prp1)\n+{\n+ NvmeCmd *phys_sqe = &sq->phys_sqe[sq->tail];\n+\n+ if (((sq->tail + 1) % sq->common.size) == sq->head) {\n+ /* no space in SQ */\n+ g_test_message(\"%s head %d tail %d\", __func__, sq->head, sq->tail);\n+ g_assert(false);\n+ return NULL;\n+ }\n+\n+ qtest_memset(sq->common.ctrl->pdev->bus->qts,\n+ (uint64_t)phys_sqe, 0, sizeof(*phys_sqe));\n+\n+ #define GUEST_MEM_WRITE(fn, field, val) \\\n+ fn(sq->common.ctrl->pdev->bus->qts, (uint64_t)&(field), (val))\n+\n+ GUEST_MEM_WRITE(qtest_writeb, phys_sqe->opcode, opcode);\n+ GUEST_MEM_WRITE(qtest_writew, phys_sqe->cid, cid);\n+ GUEST_MEM_WRITE(qtest_writeq, phys_sqe->dptr.prp1, (uint32_t)(uint64_t)prp1);\n+\n+ #undef GUEST_MEM_WRITE\n+\n+ g_test_message(\"sq %p next_sqe %u sqe %p\", sq, sq->tail, phys_sqe);\n+ return phys_sqe;\n+}\n+\n+static void nvme_commit_sqe(nvme_sq *sq)\n+{\n+ g_test_message(\"sq %p commit sqe tail %u\", sq, sq->tail);\n+ sq->tail = (sq->tail + 1) % sq->common.size;\n+ qpci_io_writel(sq->common.ctrl->pdev, sq->common.ctrl->bar, sq->common.doorbell, sq->tail);\n+}\n+\n+static NvmeIdCtrl *nvme_admin_identify_ctrl(nvme_ctrl *ctrl, uint16_t cid, bool no_wait)\n+{\n+ NvmeCmd *phys_cmd_identify;\n+ NvmeIdCtrl *phys_identify;\n+ NvmeCqe cqe;\n+\n+ g_test_message(\"sending req cid %u no_wait %d\", cid, no_wait);\n+\n+ phys_identify = (typeof(phys_identify))guest_alloc(ctrl->alloc, PAGE_SIZE);\n+ g_assert(phys_identify);\n+\n+ phys_cmd_identify = nvme_get_next_sqe(&ctrl->admin_sq,\n+ NVME_ADM_CMD_IDENTIFY, cid,\n+ phys_identify);\n+ g_assert(phys_cmd_identify);\n+\n+ #define GUEST_MEM_WRITE(fn, field, val) \\\n+ fn(ctrl->pdev->bus->qts, (uint64_t)&(field), (val))\n+\n+ GUEST_MEM_WRITE(qtest_writel, phys_cmd_identify->nsid, 0);\n+ GUEST_MEM_WRITE(qtest_writel, ((NvmeIdentify *)phys_cmd_identify)->cns, NVME_ID_CNS_CTRL);\n+\n+ #undef GUEST_MEM_WRITE\n+\n+ nvme_commit_sqe(&ctrl->admin_sq);\n+\n+ if (no_wait) {\n+ return phys_identify;\n+ }\n+\n+ cqe = nvme_wait(&ctrl->admin_sq);\n+ g_assert(nvme_is_cqe_success(&cqe));\n+ g_assert(cqe.cid == cid);\n+\n+ return phys_identify;\n+}\n+\n+static void nvme_wait_ready(nvme_ctrl *ctrl, int val)\n+{\n+ int i;\n+\n+ for (i = 0; i < 10; i++) {\n+ uint32_t csts = qpci_io_readl(ctrl->pdev, ctrl->bar, NVME_REG_CSTS);\n+ g_test_message(\"%s: csts %x\", __func__, csts);\n+\n+ if (NVME_CSTS_RDY(csts) == val) {\n+ return;\n+ }\n+\n+ g_usleep(1000);\n+ }\n+\n+ g_assert(false);\n+}\n+\n+static void test_migrate_setup_nvme_ctrl(nvme_ctrl *ctrl)\n+{\n+ uint64_t cap;\n+\n+ /* disable controller */\n+ qpci_io_writel(ctrl->pdev, ctrl->bar, NVME_REG_CC, 0);\n+ nvme_wait_ready(ctrl, 0);\n+\n+ cap = qpci_io_readq(ctrl->pdev, ctrl->bar, NVME_REG_CAP);\n+ ctrl->db_stride = 4 << NVME_CAP_DSTRD(cap);\n+\n+ nvme_init_cq(ctrl, &ctrl->admin_cq, 1, 2 /* CQEs num */);\n+ nvme_init_sq(ctrl, &ctrl->admin_sq, 0, 4 /* SQEs num */, &ctrl->admin_cq);\n+\n+ qpci_io_writel(ctrl->pdev, ctrl->bar, NVME_REG_AQA,\n+ ((ctrl->admin_cq.common.size - 1) << AQA_ACQS_SHIFT) |\n+ ((ctrl->admin_sq.common.size - 1) << AQA_ASQS_SHIFT)\n+ );\n+\n+ qpci_io_writeq(ctrl->pdev, ctrl->bar,\n+ NVME_REG_ASQ, (uint64_t)ctrl->admin_sq.phys_sqe);\n+ qpci_io_writeq(ctrl->pdev, ctrl->bar,\n+ NVME_REG_ACQ, (uint64_t)ctrl->admin_cq.phys_cqe);\n+\n+ /* enable controller */\n+ {\n+ uint32_t cc = 0;\n+ NVME_SET_CC_EN(cc, 1);\n+ qpci_io_writel(ctrl->pdev, ctrl->bar, NVME_REG_CC, cc);\n+ }\n+\n+ nvme_wait_ready(ctrl, 1);\n+}\n+\n+typedef struct test_migrate_req {\n+ uint16_t cid;\n+ bool handle_cqe;\n+ NvmeIdCtrl *phys_identify;\n+} test_migrate_req;\n+\n+static void test_migrate_send_nvme_reqs(nvme_ctrl *ctrl, test_migrate_req *reqs,\n+ int num)\n+{\n+ int i;\n+\n+ for (i = 0; i < num; i++) {\n+ reqs[i].phys_identify = nvme_admin_identify_ctrl(ctrl, reqs[i].cid,\n+ !reqs[i].handle_cqe);\n+ g_assert(reqs[i].phys_identify);\n+\n+ if (reqs[i].handle_cqe) {\n+ guest_free(ctrl->alloc, (uint64_t)reqs[i].phys_identify);\n+ }\n+ }\n+}\n+\n+static void test_migrate_check_nvme(nvme_ctrl *ctrl, test_migrate_req *reqs, int num)\n+{\n+ int i;\n+\n+ for (i = 0; i < num; i++) {\n+ NvmeCqe cqe;\n+\n+ if (reqs[i].handle_cqe) {\n+ continue;\n+ }\n+\n+ cqe = nvme_wait(&ctrl->admin_sq);\n+ g_assert(nvme_is_cqe_success(&cqe));\n+\n+ g_assert_cmpint(cqe.cid, ==, reqs[i].cid);\n+\n+ #define GUEST_MEM_READB(field) \\\n+ qtest_readb(ctrl->pdev->bus->qts, (uint64_t)&(field))\n+\n+ g_assert_cmpint(GUEST_MEM_READB(reqs[i].phys_identify->ieee[0]), ==, 0x0);\n+ g_assert_cmpint(GUEST_MEM_READB(reqs[i].phys_identify->ieee[1]), ==, 0x54);\n+ g_assert_cmpint(GUEST_MEM_READB(reqs[i].phys_identify->ieee[2]), ==, 0x52);\n+\n+ #undef GUEST_MEM_READB\n+\n+ guest_free(ctrl->alloc, (uint64_t)reqs[i].phys_identify);\n+ }\n+}\n+\n+static void test_migrate(void *obj, void *data, QGuestAllocator *alloc)\n+{\n+ g_autofree gchar *tmpfs = NULL;\n+ GError *err = NULL;\n+ g_autofree gchar *mig_path;\n+ g_autofree gchar *uri;\n+ GString *dest_cmdline;\n+ QTestState *to;\n+ QDict *rsp;\n+ QNvme *nvme = obj;\n+ QPCIDevice *pdev = &nvme->dev;\n+ nvme_ctrl *ctrl;\n+ test_migrate_req test_reqs[] = {\n+ { 123, true },\n+ { 456, false },\n+ { 300, false },\n+ { 333, false }\n+ };\n+\n+ /* create temporary dir and prepare unix socket path for migration */\n+ tmpfs = g_dir_make_tmp(\"nvme-test-XXXXXX\", &err);\n+ if (!tmpfs) {\n+ g_test_message(\"Can't create temporary directory in %s: %s\",\n+ g_get_tmp_dir(), err->message);\n+ g_error_free(err);\n+ }\n+ g_assert(tmpfs);\n+\n+ mig_path = g_strdup_printf(\"%s/socket.mig\", tmpfs);\n+ uri = g_strdup_printf(\"unix:%s\", mig_path);\n+\n+ /* enable NVMe PCI device */\n+ qpci_device_enable(pdev);\n+\n+ ctrl = g_malloc0(sizeof(*ctrl));\n+ ctrl->alloc = alloc;\n+ ctrl->pdev = pdev;\n+ ctrl->bar = qpci_iomap(ctrl->pdev, 0, NULL);\n+ g_assert(pdev->bus->qts == global_qtest);\n+\n+ test_migrate_setup_nvme_ctrl(ctrl);\n+ test_migrate_send_nvme_reqs(ctrl, test_reqs, ARRAY_SIZE(test_reqs));\n+\n+ qpci_iounmap(ctrl->pdev, ctrl->bar);\n+\n+ dest_cmdline = g_string_new(qos_get_current_command_line());\n+ g_string_append_printf(dest_cmdline, \" -incoming %s\", uri);\n+\n+ /* Create destination VM */\n+ to = qtest_init(dest_cmdline->str);\n+\n+ /* Get access to PCI device from destination VM */\n+ nvme = qos_allocate_objects(to, &ctrl->alloc);\n+ pdev = &nvme->dev;\n+ ctrl->pdev = pdev;\n+ ctrl->bar = qpci_iomap(ctrl->pdev, 0, NULL);\n+ g_assert(pdev->bus->qts == to);\n+\n+ /* Migrate VM */\n+ rsp = qmp(\"{ 'execute': 'migrate', 'arguments': { 'uri': %s } }\", uri);\n+ g_assert(qdict_haskey(rsp, \"return\"));\n+ qobject_unref(rsp);\n+\n+ /* Wait when source VM is stopped */\n+ qmp_eventwait(\"STOP\");\n+\n+ /* Copy guest physical memory allocator state */\n+ migrate_allocator(alloc, ctrl->alloc);\n+\n+ /* Wait for destination VM to become alive */\n+ qtest_qmp_eventwait(to, \"RESUME\");\n+\n+ test_migrate_check_nvme(ctrl, test_reqs, ARRAY_SIZE(test_reqs));\n+\n+ qpci_iounmap(ctrl->pdev, ctrl->bar);\n+\n+ qtest_quit(to);\n+ g_unlink(mig_path);\n+ g_rmdir(tmpfs);\n+ g_string_free(dest_cmdline, true);\n+}\n+\n static void nvme_register_nodes(void)\n {\n QOSGraphEdgeOptions opts = {\n@@ -168,6 +559,8 @@ static void nvme_register_nodes(void)\n });\n \n qos_add_test(\"reg-read\", \"nvme\", nvmetest_reg_read_test, NULL);\n+\n+ qos_add_test(\"migrate\", \"nvme\", test_migrate, NULL);\n }\n \n libqos_init(nvme_register_nodes);\n", "prefixes": [ "v6", "8/8" ] }