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GET /api/1.1/patches/2224695/?format=api
{ "id": 2224695, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2224695/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260417184012.2875033-1-pengxuan.zheng@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260417184012.2875033-1-pengxuan.zheng@oss.qualcomm.com>", "date": "2026-04-17T18:40:12", "name": "aarch64: Recognize vector permute patterns which can be optimized as REV64+EXT [PR102055]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6c0d92398dd263628a1bec85c8a230d36f71a93c", "submitter": { "id": 92245, "url": "http://patchwork.ozlabs.org/api/1.1/people/92245/?format=api", "name": "Pengxuan Zheng", "email": "pengxuan.zheng@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260417184012.2875033-1-pengxuan.zheng@oss.qualcomm.com/mbox/", "series": [ { "id": 500387, "url": "http://patchwork.ozlabs.org/api/1.1/series/500387/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500387", "date": "2026-04-17T18:40:12", "name": "aarch64: Recognize vector permute patterns which can be optimized as REV64+EXT [PR102055]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500387/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224695/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224695/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ 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<pengxuan.zheng@oss.qualcomm.com>", "To": "gcc-patches@gcc.gnu.org", "Subject": "[PATCH] aarch64: Recognize vector permute patterns which can be\n optimized as REV64+EXT [PR102055]", "Date": "Fri, 17 Apr 2026 11:40:12 -0700", "Message-Id": "<20260417184012.2875033-1-pengxuan.zheng@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "rhJgqzsJraNzISpxjc7JGq1y9Eokz70E", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDE3MDE4NyBTYWx0ZWRfX6r+oL9Z/sKvg\n ahCVA75X1V2gYS05lX1EkVr30xLKcnu9eYpE2GjhBIds4zU9QdNacNWlLLQU/U6HOusRU8iYSNx\n id28A5Tw3+36jFMGVidYlxI0MGXODjCUhul/rFKqfr5Ko5g/T5aH9xOOQNVMRLC3+m2wpwHI7d2\n iuqT2cAkuDGHnOl/8keqv4PxPs2cXpr4k4IXwmoY1DdHuwE7yEhkKAor1TNdOk2PHh8Ay9AOFoz\n KeFLqc7L3v4SZ6z1iVruWr/9AYf7qqrF4AKRAJC0E5zjKKi8wbjJszGMfJ0h9JOgLC5ti+gogY6\n IW3V3DFWIIMSLdS18s5mUlKN/tyD5UVXKCb/BqCDb2TsYPXxF5PN16d/6TlWLUeSm4MXPstFd5/\n u7QuAwdFH9pz7c9zgXRYrIctG6SxcO+k/Hontzt+86399R6nJJjmqwqtJ0Ioabs3m4TudO6cr1M\n 0CSZo+8Pqs0WoAl5t7A==", "X-Authority-Analysis": "v=2.4 cv=X+Fi7mTe c=1 sm=1 tr=0 ts=69e27e8f cx=c_pps\n a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8\n a=PDIdRR9ASaOTMW4Umo4A:9 a=6Ab_bkdmUrQuMsNx7PHu:22", "X-Proofpoint-GUID": "rhJgqzsJraNzISpxjc7JGq1y9Eokz70E", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n phishscore=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0\n bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170187", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Currently, with Advanced SIMD\n\nvector char\nf (vector char a)\n{\n return __builtin_shuffle (a, (vector char){ 15, 14, 13, 12, 11, 10, 9, 8,\n\t\t\t\t\t 7, 6, 5, 4, 3, 2, 1, 0 });\n}\n\ngenerates:\n\nf:\n\tadrp\tx0, .LANCHOR0\n\tldr\tq31, [x0, #:lo12:.LANCHOR0]\n\ttbl\tv0.16b, {v0.16b}, v31.16b\n\tret\n\t.set\t.LANCHOR0,. + 0\n\t.LC0:\n\t.byte\t15\n\t.byte\t14\n\t.byte\t13\n\t.byte\t12\n\t.byte\t11\n\t.byte\t10\n\t.byte\t9\n\t.byte\t8\n\t.byte\t7\n\t.byte\t6\n\t.byte\t5\n\t.byte\t4\n\t.byte\t3\n\t.byte\t2\n\t.byte\t1\n\t.byte\t0\n\nWith this patch, it generates REV64 followed by EXT:\n\nf:\n\trev64\tv0.16b, v0.16b\n\text\tv0.16b, v0.16b, v0.16b, #8\n\tret\n\nBootstrapped and tested on aarch64_linux_gnu.\n\n\tPR target/102055\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64.cc (aarch64_evpc_rev64_ext): New.\n\t(aarch64_expand_vec_perm_const_1): Call aarch64_evpc_rev64_ext.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/pr102055.c: New test.\n\nSigned-off-by: Pengxuan Zheng <pengxuan.zheng@oss.qualcomm.com>\n---\n gcc/config/aarch64/aarch64.cc | 32 ++++++++++++++++\n gcc/testsuite/gcc.target/aarch64/pr102055.c | 42 +++++++++++++++++++++\n 2 files changed, 74 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/pr102055.c", "diff": "diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 62194b96450..5fdb1a42c99 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -27714,6 +27714,36 @@ aarch64_evpc_rev_global (struct expand_vec_perm_d *d)\n return true;\n }\n \n+/* Recognize patterns for the Advanced SIMD REV64 + EXT insns, which reverse\n+ elements within a full vector. */\n+\n+static bool\n+aarch64_evpc_rev64_ext (struct expand_vec_perm_d *d)\n+{\n+ poly_uint64 nelt = d->perm.length ();\n+\n+ if (!d->one_vector_p || d->vec_flags != VEC_ADVSIMD)\n+ return false;\n+\n+ if (!d->perm.series_p (0, 1, nelt - 1, -1))\n+ return false;\n+\n+ if (d->testing_p)\n+ return true;\n+\n+ rtx tmp1 = gen_reg_rtx (d->vmode);\n+ rtx tmp2 = gen_reg_rtx (V16QImode);\n+ rtx unspec_rev64\n+ = gen_rtx_UNSPEC (d->vmode, gen_rtvec (1, d->op0), UNSPEC_REV64);\n+ emit_set_insn (tmp1, unspec_rev64);\n+ rtvec vec = gen_rtvec (3, gen_lowpart (V16QImode, tmp1),\n+\t\t\t gen_lowpart (V16QImode, tmp1), GEN_INT (8));\n+ rtx unspec_ext = gen_rtx_UNSPEC (V16QImode, vec, UNSPEC_EXT);\n+ emit_set_insn (tmp2, unspec_ext);\n+ emit_set_insn (d->target, gen_lowpart (d->vmode, tmp2));\n+ return true;\n+}\n+\n static bool\n aarch64_evpc_dup (struct expand_vec_perm_d *d)\n {\n@@ -28175,6 +28205,8 @@ aarch64_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)\n \t return true;\n \t else if (aarch64_evpc_hvla (d))\n \t return true;\n+\t else if (aarch64_evpc_rev64_ext (d))\n+\t return true;\n \t else if (aarch64_evpc_reencode (d))\n \t return true;\n \ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr102055.c b/gcc/testsuite/gcc.target/aarch64/pr102055.c\nnew file mode 100644\nindex 00000000000..39b6355fc66\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr102055.c\n@@ -0,0 +1,42 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-final { check-function-bodies \"**\" \"\" \"\" } } */\n+\n+#define vector __attribute__ ((vector_size (16)))\n+\n+/*\n+** f:\n+**\trev64\tv([0-9]+).16b, v0.16b\n+**\text\tv0.16b, v\\1.16b, v\\1.16b, #8\n+**\tret\n+*/\n+vector char\n+f (vector char a)\n+{\n+ return __builtin_shuffle (a, (vector char){ 15, 14, 13, 12, 11, 10, 9, 8,\n+\t\t\t\t\t 7, 6, 5, 4, 3, 2, 1, 0 });\n+}\n+\n+/*\n+** f1:\n+**\trev64\tv([0-9]+).8h, v0.8h\n+**\text\tv0.16b, v\\1.16b, v\\1.16b, #8\n+**\tret\n+*/\n+vector short\n+f1 (vector short a)\n+{\n+ return __builtin_shuffle (a, (vector short){ 7, 6, 5, 4, 3, 2, 1, 0 });\n+}\n+\n+/*\n+** f2:\n+**\trev64\tv([0-9]+).4s, v0.4s\n+**\text\tv0.16b, v\\1.16b, v\\1.16b, #8\n+**\tret\n+*/\n+vector int\n+f2 (vector int a)\n+{\n+ return __builtin_shuffle (a, (vector int){ 3, 2, 1, 0 });\n+}\n", "prefixes": [] }