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GET /api/1.1/patches/2223870/?format=api
{ "id": 2223870, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223870/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260416093041.42070-2-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260416093041.42070-2-fengchengwen@huawei.com>", "date": "2026-04-16T09:30:37", "name": "[v2,RESEND,1/5] pci/tph: Export pcie_tph_get_st_modes() for external use", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "aa2d02f7f456dd7a1bdeb3ea114f70044f6833e6", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.1/people/92756/?format=api", "name": "Chengwen Feng", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260416093041.42070-2-fengchengwen@huawei.com/mbox/", "series": [ { "id": 500126, "url": "http://patchwork.ozlabs.org/api/1.1/series/500126/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500126", "date": "2026-04-16T09:30:36", "name": "vfio/pci: Add PCIe TPH support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500126/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223870/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223870/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52591-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=4mP4rr0Q;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52591-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"4mP4rr0Q\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.220", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxCbT1NrCz1yG9\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 16 Apr 2026 19:37:25 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id DAF4231E34B3\n\tfor <incoming@patchwork.ozlabs.org>; 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Thu, 16 Apr 2026 17:30:47 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776331857; cv=none;\n b=pZa2ijocJsm6+1kYhRVa2kxf2S/e2RGU0/LJwcA71MUJYSrfHYZvvxnuc3tdpa6ORbwcB+VSHyYIlzmUhpbJBEhTG12uOcSzngpso301WVK97pEbGfIaDOYiqd+xX6MRhwdDv3ntPffPw9tQfJxpEVn8i6QMU2gfsvJJZi7NBk4=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776331857; c=relaxed/simple;\n\tbh=L0DmendFOefQPFtDMYKcMhHvE4IfubXJSzqUkPf7WoU=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=nyRv3KQzC3z3LUTyXPwqy4fdXGjIyexI0FZJ8ucaZCAa/4lUMPvdRtTx5+o41E0hjuZImOuSK4nJfEikS2N62pdDVvzpsBZkIReEGOf/GcPghS9n4wY7BkI41joRt2dkcCy8qeIXKj+d51uJ7x4MJp0YU1q/1/ezy9WFqsYlmeU=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=4mP4rr0Q; arc=none smtp.client-ip=113.46.200.220", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=fvtU7x+vm6WEZqPSyBi3XSd/2T89n1LNpBCVUXCkqbs=;\n\tb=4mP4rr0QnLvnEdOygZZ7JKQ4n0G8fqcpMsmwTEHFM++6EKGHHWOcwkNu+xsn8Za7SXwzIPgUW\n\tJZx+v/vukr08JvXXnHZ5nJJh81YemT+4IWFyYmsW1uqo8zfI81h0cO3R4wx2CAwTzbTKaAG2AsK\n\tmcpRVDYAVZWl3J8wzETa1fY=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <wangzhou1@hisilicon.com>,\n\t<wangyushan12@huawei.com>, <liuyonglong@huawei.com>, <kvm@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>", "Subject": "[PATCH v2 RESEND 1/5] pci/tph: Export pcie_tph_get_st_modes() for\n external use", "Date": "Thu, 16 Apr 2026 17:30:37 +0800", "Message-ID": "<20260416093041.42070-2-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260416093041.42070-1-fengchengwen@huawei.com>", "References": "<20260416093041.42070-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems200002.china.huawei.com (7.221.188.68) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Export the helper to retrieve supported PCIe TPH steering tag modes so\nthat drivers like VFIO can query and expose device capabilities to\nuserspace.\n\nAnd also add pcie_tph_get_st_table_size() and\npcie_tph_get_st_table_loc() stub implementation in the !CONFIG_PCI_TPH\ncase.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/pci/tph.c | 13 +++++++++++--\n include/linux/pci-tph.h | 7 +++++++\n 2 files changed, 18 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/tph.c b/drivers/pci/tph.c\nindex 91145e8d9d95..f8767bf6fee9 100644\n--- a/drivers/pci/tph.c\n+++ b/drivers/pci/tph.c\n@@ -145,7 +145,15 @@ static void set_ctrl_reg_req_en(struct pci_dev *pdev, u8 req_type)\n \tpci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);\n }\n \n-static u8 get_st_modes(struct pci_dev *pdev)\n+/**\n+ * pcie_tph_get_st_modes - Get supported Steering Tag modes\n+ * @pdev: PCI device to query\n+ *\n+ * Return:\n+ * Bitmask of supported ST modes (PCI_TPH_CAP_ST_NS, PCI_TPH_CAP_ST_IV,\n+ * PCI_TPH_CAP_ST_DS)\n+ */\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n {\n \tu32 reg;\n \n@@ -154,6 +162,7 @@ static u8 get_st_modes(struct pci_dev *pdev)\n \n \treturn reg;\n }\n+EXPORT_SYMBOL(pcie_tph_get_st_modes);\n \n /**\n * pcie_tph_get_st_table_loc - Return the device's ST table location\n@@ -400,7 +409,7 @@ int pcie_enable_tph(struct pci_dev *pdev, int mode)\n \n \t/* Sanitize and check ST mode compatibility */\n \tmode &= PCI_TPH_CTRL_MODE_SEL_MASK;\n-\tdev_modes = get_st_modes(pdev);\n+\tdev_modes = pcie_tph_get_st_modes(pdev);\n \tif (!((1 << mode) & dev_modes))\n \t\treturn -EINVAL;\n \ndiff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h\nindex be68cd17f2f8..586c75b19e01 100644\n--- a/include/linux/pci-tph.h\n+++ b/include/linux/pci-tph.h\n@@ -30,6 +30,7 @@ void pcie_disable_tph(struct pci_dev *pdev);\n int pcie_enable_tph(struct pci_dev *pdev, int mode);\n u16 pcie_tph_get_st_table_size(struct pci_dev *pdev);\n u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev);\n+u8 pcie_tph_get_st_modes(struct pci_dev *pdev);\n #else\n static inline int pcie_tph_set_st_entry(struct pci_dev *pdev,\n \t\t\t\t\tunsigned int index, u16 tag)\n@@ -41,6 +42,12 @@ static inline int pcie_tph_get_cpu_st(struct pci_dev *dev,\n static inline void pcie_disable_tph(struct pci_dev *pdev) { }\n static inline int pcie_enable_tph(struct pci_dev *pdev, int mode)\n { return -EINVAL; }\n+static inline u16 pcie_tph_get_st_table_size(struct pci_dev *pdev)\n+{ return 0; }\n+static inline u32 pcie_tph_get_st_table_loc(struct pci_dev *pdev)\n+{ return 0x7FF; /* Values that do not appear in normal case */ }\n+static inline u8 pcie_tph_get_st_modes(struct pci_dev *pdev)\n+{ return 0; }\n #endif\n \n #endif /* LINUX_PCI_TPH_H */\n", "prefixes": [ "v2", "RESEND", "1/5" ] }