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GET /api/1.1/patches/2223844/?format=api
{ "id": 2223844, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223844/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260416092105.41439-4-fengchengwen@huawei.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260416092105.41439-4-fengchengwen@huawei.com>", "date": "2026-04-16T09:21:03", "name": "[v2,3/5] vfio/pci: Add PCIe TPH enable/disable support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "86ef9ab6f4af56ea96fac31d5c18d9c906bb15dd", "submitter": { "id": 92756, "url": "http://patchwork.ozlabs.org/api/1.1/people/92756/?format=api", "name": "Chengwen Feng", "email": "fengchengwen@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260416092105.41439-4-fengchengwen@huawei.com/mbox/", "series": [ { "id": 500123, "url": "http://patchwork.ozlabs.org/api/1.1/series/500123/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500123", "date": "2026-04-16T09:21:03", "name": "vfio/pci: Add PCIe TPH support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500123/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223844/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223844/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52579-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=huawei.com header.i=@huawei.com header.a=rsa-sha256\n header.s=dkim header.b=qYhdb+kc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-52579-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=\"qYhdb+kc\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=113.46.200.225", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=huawei.com" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org\n [IPv6:2600:3c09:e001:a7::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxCG82cnxz1yG9\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 16 Apr 2026 19:22:24 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 86BE7306A18D\n\tfor <incoming@patchwork.ozlabs.org>; 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Thu, 16 Apr 2026 17:21:12 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776331277; cv=none;\n b=RO+CzrZ+vxSKXbfl++CkGNXch7v7gWvvbBjluNY4nkdv+UD4BNoXlaGG840xG7mLGGdwi/+zzaP8yZEzwlUgGz7vP8KyjgiIWFJSHvBNpUBrWDOuY5EAKl1AWVDwFtNzwbJefwJAyzSq9Q10DiQ2wBFu5tR+1eeFs6+2U3M5tos=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776331277; c=relaxed/simple;\n\tbh=RNwAGTBMpzwEr+myWRaeoZSPWXsAexs+BUjnA0eZ03I=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=IrIPHnKoKWD81GRzeOgixuW3zFPLBSU71A+UDpbUQqckOAOWIG9Z40CX1CWmNskQihSiu+BOU6fF81yZHgrF4aTUe4E/0W1NirCFn3y6ciRuTWS88nnnV4FxvmZyASYTD4FPXrnQPC8zJ459ObDwsKihlOqWa7bTTOP4Md//SVk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=huawei.com;\n spf=pass smtp.mailfrom=huawei.com;\n dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com\n header.b=qYhdb+kc; arc=none smtp.client-ip=113.46.200.225", "dkim-signature": "v=1; a=rsa-sha256; d=huawei.com; s=dkim;\n\tc=relaxed/relaxed; q=dns/txt;\n\th=From;\n\tbh=Vm6GVTHIjg7srtzmpwKRJWxW+mbYdqCyts7eyl/ruek=;\n\tb=qYhdb+kcJczbWaGsLeFOtykT+gMGaRbGygNdtXDrnboXqihEtNDfSzV43nDgpp2Nsoe4WuF6W\n\tvK2rP4HwYDZphx1Gc3yrMEw7dVSj2bnwpqO9yFwn7X3e7sEHp3LV2h0S2VTCoN1OqQBhAwqTi5x\n\tD9pEt/VLPJYO7mpGysztt0I=", "From": "Chengwen Feng <fengchengwen@huawei.com>", "To": "<alex@shazbot.org>, <jgg@ziepe.ca>", "CC": "<wathsala.vithanage@arm.com>, <wangzhou1@hisilicon.com>,\n\t<wangyushan12@huawei.com>, <liuyonglong@huawei.com>, <kvm@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>", "Subject": "[PATCH v2 3/5] vfio/pci: Add PCIe TPH enable/disable support", "Date": "Thu, 16 Apr 2026 17:21:03 +0800", "Message-ID": "<20260416092105.41439-4-fengchengwen@huawei.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20260416092105.41439-1-fengchengwen@huawei.com>", "References": "<20260416092105.41439-1-fengchengwen@huawei.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-ClientProxiedBy": "kwepems200002.china.huawei.com (7.221.188.68) To\n kwepemk500009.china.huawei.com (7.202.194.94)" }, "content": "Add support to enable and disable TPH function with\nmode selection.\n\nSigned-off-by: Chengwen Feng <fengchengwen@huawei.com>\n---\n drivers/vfio/pci/vfio_pci_core.c | 36 ++++++++++++++++++++++++++++++++\n 1 file changed, 36 insertions(+)", "diff": "diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c\nindex fc82ab845737..22c16662f533 100644\n--- a/drivers/vfio/pci/vfio_pci_core.c\n+++ b/drivers/vfio/pci/vfio_pci_core.c\n@@ -1487,6 +1487,38 @@ static int vfio_pci_tph_get_cap(struct vfio_pci_core_device *vdev,\n \treturn 0;\n }\n \n+static int vfio_pci_tph_enable(struct vfio_pci_core_device *vdev,\n+\t\t\t struct vfio_device_pci_tph_op *op,\n+\t\t\t void __user *uarg)\n+{\n+\tstruct vfio_pci_tph_ctrl ctrl;\n+\tint mode;\n+\n+\tif (op->argsz < offsetofend(struct vfio_device_pci_tph_op, ctrl))\n+\t\treturn -EINVAL;\n+\n+\tif (copy_from_user(&ctrl, uarg, sizeof(ctrl)))\n+\t\treturn -EFAULT;\n+\n+\tif (ctrl.mode != VFIO_PCI_TPH_MODE_IV &&\n+\t ctrl.mode != VFIO_PCI_TPH_MODE_DS)\n+\t\treturn -EINVAL;\n+\n+\t/* Reserved must be zero */\n+\tif (memchr_inv(ctrl.reserved, 0, sizeof(ctrl.reserved)))\n+\t\treturn -EINVAL;\n+\n+\tmode = (ctrl.mode == VFIO_PCI_TPH_MODE_IV) ? PCI_TPH_ST_IV_MODE :\n+\t\t\t\t\t\t PCI_TPH_ST_DS_MODE;\n+\treturn pcie_enable_tph(vdev->pdev, mode);\n+}\n+\n+static int vfio_pci_tph_disable(struct vfio_pci_core_device *vdev)\n+{\n+\tpcie_disable_tph(vdev->pdev);\n+\treturn 0;\n+}\n+\n static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \t\t\t void __user *uarg)\n {\n@@ -1503,6 +1535,10 @@ static int vfio_pci_ioctl_tph(struct vfio_pci_core_device *vdev,\n \tswitch (op.op) {\n \tcase VFIO_PCI_TPH_GET_CAP:\n \t\treturn vfio_pci_tph_get_cap(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_ENABLE:\n+\t\treturn vfio_pci_tph_enable(vdev, &op, uarg + minsz);\n+\tcase VFIO_PCI_TPH_DISABLE:\n+\t\treturn vfio_pci_tph_disable(vdev);\n \tdefault:\n \t\t/* Other ops are not implemented yet */\n \t\treturn -EINVAL;\n", "prefixes": [ "v2", "3/5" ] }