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GET /api/1.1/patches/2223794/?format=api
{ "id": 2223794, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223794/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260416083442.2056-1-tanshanshan@eswincomputing.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260416083442.2056-1-tanshanshan@eswincomputing.com>", "date": "2026-04-16T08:34:41", "name": "[arm] Enable stm_case=5 in store_multiple_sequence", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "43626bf3dbd74dff72715249132e0ced5ea4472d", "submitter": { "id": 92555, "url": "http://patchwork.ozlabs.org/api/1.1/people/92555/?format=api", "name": "覃珊珊", "email": "tanshanshan@eswincomputing.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260416083442.2056-1-tanshanshan@eswincomputing.com/mbox/", "series": [ { "id": 500108, "url": "http://patchwork.ozlabs.org/api/1.1/series/500108/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=500108", "date": "2026-04-16T08:34:41", "name": "[arm] Enable stm_case=5 in store_multiple_sequence", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/500108/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223794/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223794/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org", "From": "tanshanshan <tanshanshan@eswincomputing.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "Richard.Earnshaw@arm.com, kito.cheng@gmail.com, palmer@dabbelt.com,\n jeffreyalaw@gmail.com, tanshanshan@eswincomputing.com", "Subject": "[PATCH] [arm] Enable stm_case=5 in store_multiple_sequence", "Date": "Thu, 16 Apr 2026 16:34:41 +0800", "Message-ID": "<20260416083442.2056-1-tanshanshan@eswincomputing.com>", "X-Mailer": "git-send-email 2.47.1.windows.2", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "TQJkCgAXLaAjn+BprCISAA--.10959S2", "X-Coremail-Antispam": "1UD129KBjvJXoWxAFyrtr4DCF43ur43KryxAFb_yoW5GrW8pr\n s7Gw43tryxGF4fAFyDZFWkXFyUurs3Kw12kr9xKFZrA343trWIka1qkFn093W3WrWUAr43\n Xrn8Jr4Y9w1Du3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUvS14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02\n 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U\n JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc\n CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E\n 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV\n W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_\n JF0_Jw1lc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI\n 8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AK\n xVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI\n 8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280\n aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43\n ZEXa7VUbb_-PUUUUU==", "X-CM-SenderInfo": "pwdq2xxdqvxt3q6h245lqf0zpsxwx03jof0z/", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "The load_multiple_sequence function already supports ldm_case=5 to handle\nmemory references with arbitrary ARM-encodable constant offsets (via\nconst_ok_for_arm). However, the corresponding store path in\nstore_multiple_sequence lacked this capability, even though gen_stm_seq\nwas prepared to handle stm_case=5.\n\nThe change adds a check similar to load_multiple_sequence: when the\noffset is not zero but can be encoded as an ARM immediate (using\nconst_ok_for_arm), we now return stm_case = 5. This enables the\ngeneration of add+stm sequences for store operations, improving\ncode size and maintaining consistency between load and store\noptimizations.\n\ngcc/ChangeLog:\n * config/arm/arm.c (store_multiple_sequence): Add support for\n stm_case=5 using const_ok_for_arm to check offset encodability.\n\nSigned-off-by: tanshanshan <tanshanshan@eswincomputing.com>\n---\n gcc/config/arm/arm.cc | 22 ++++++++++++++++++----\n 1 file changed, 18 insertions(+), 4 deletions(-)", "diff": "diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc\nindex 0a1f6612d07..c03dde91ab9 100644\n--- a/gcc/config/arm/arm.cc\n+++ b/gcc/config/arm/arm.cc\n@@ -14907,9 +14907,19 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,\n stm_case = 3; /* stmda */\n else if (TARGET_32BIT && unsorted_offsets[order[nops - 1]] == -4)\n stm_case = 4; /* stmdb */\n+ else if (const_ok_for_arm (unsorted_offsets[order[0]])\n+\t || const_ok_for_arm (-unsorted_offsets[order[0]]))\n+ stm_case = 5;\n else\n return 0;\n \n+ if (stm_case == 5){\n+ for (i = 0; i < nops; i++){\n+ if (unsorted_regs[i] == base_reg)\n+ return 0;\n+ }\n+ }\n+\n if (!multiple_operation_profitable_p (false, nops, 0))\n return 0;\n \n@@ -15169,13 +15179,15 @@ gen_stm_seq (rtx *operands, int nops)\n base_reg_dies = peep2_reg_dead_p (nops, base_reg_rtx);\n if (TARGET_THUMB1)\n {\n- gcc_assert (base_reg_dies);\n+ if (base_reg_dies)\n+ return false;\n write_back = TRUE;\n }\n \n if (stm_case == 5)\n {\n- gcc_assert (base_reg_dies);\n+ if (base_reg_dies)\n+ return false;\n emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));\n offset = 0;\n }\n@@ -15285,13 +15297,15 @@ gen_const_stm_seq (rtx *operands, int nops)\n base_reg_dies = peep2_reg_dead_p (nops * 2, base_reg_rtx);\n if (TARGET_THUMB1)\n {\n- gcc_assert (base_reg_dies);\n+ if (base_reg_dies)\n+ return false;\n write_back = TRUE;\n }\n \n if (stm_case == 5)\n {\n- gcc_assert (base_reg_dies);\n+ if (base_reg_dies)\n+ return false;\n emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, GEN_INT (offset)));\n offset = 0;\n }\n", "prefixes": [ "arm" ] }