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GET /api/1.1/patches/2223235/?format=api
{ "id": 2223235, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223235/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414182313.1691519-11-gaurav.sharma_7@nxp.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260414182313.1691519-11-gaurav.sharma_7@nxp.com>", "date": "2026-04-14T18:23:08", "name": "[PATCHv6,10/15] hw/arm/fsl-imx8mm: Adding support for SPI controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "356d41714f0ead47dce02dcef43bd244affc8cd5", "submitter": { "id": 92057, "url": "http://patchwork.ozlabs.org/api/1.1/people/92057/?format=api", "name": "Gaurav Sharma", "email": "gaurav.sharma_7@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414182313.1691519-11-gaurav.sharma_7@nxp.com/mbox/", "series": [ { "id": 499884, "url": "http://patchwork.ozlabs.org/api/1.1/series/499884/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499884", "date": "2026-04-14T18:23:11", "name": "Adding comprehensive support for i.MX8MM EVK board", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499884/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223235/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223235/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwCPj6MYDz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 04:25:29 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wCiQ5-0006WA-MN; Tue, 14 Apr 2026 14:23:29 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaurav.sharma_7@nxp.com>)\n id 1wCiQ2-0006Sx-2k\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 14:23:26 -0400", "from inva020.nxp.com ([92.121.34.13])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaurav.sharma_7@nxp.com>)\n id 1wCiPz-0006hM-SN\n for qemu-devel@nongnu.org; Tue, 14 Apr 2026 14:23:25 -0400", "from inva020.nxp.com (localhost [127.0.0.1])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 4CCAD1A286D;\n Tue, 14 Apr 2026 20:23:21 +0200 (CEST)", "from aprdc01srsp001v.ap-rdc01.nxp.com\n (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16])\n by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 176451A2864;\n Tue, 14 Apr 2026 20:23:21 +0200 (CEST)", "from lsv031015.swis.in-blr01.nxp.com\n (lsv031015.swis.in-blr01.nxp.com [10.12.177.77])\n by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 853791802227;\n Wed, 15 Apr 2026 02:23:20 +0800 (+08)" ], "From": "Gaurav Sharma <gaurav.sharma_7@nxp.com>", "To": "qemu-devel@nongnu.org", "Cc": "pbonzini@redhat.com, peter.maydell@linaro.org,\n Gaurav Sharma <gaurav.sharma_7@nxp.com>,\n Philippe Mathieu-Daude <philmd@linaro.org>", "Subject": "[PATCHv6 10/15] hw/arm/fsl-imx8mm: Adding support for SPI controller", "Date": "Tue, 14 Apr 2026 23:53:08 +0530", "Message-Id": "<20260414182313.1691519-11-gaurav.sharma_7@nxp.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260414182313.1691519-1-gaurav.sharma_7@nxp.com>", "References": "<20260414182313.1691519-1-gaurav.sharma_7@nxp.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Received-SPF": "pass client-ip=92.121.34.13;\n envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com", "X-Spam_score_int": "-41", "X-Spam_score": "-4.2", "X-Spam_bar": "----", "X-Spam_report": "(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "It enables emulation of ECSPI in iMX8MM\nAdded SPI IRQ lines\n\nReviewed-by: Philippe Mathieu-Daude <philmd@linaro.org>\nReviewed-by: Peter Maydell <peter.maydell@linaro.org>\nSigned-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>\n---\n hw/arm/fsl-imx8mm.c | 26 ++++++++++++++++++++++++++\n include/hw/arm/fsl-imx8mm.h | 7 +++++++\n 2 files changed, 33 insertions(+)", "diff": "diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c\nindex 3632d85197..f433beeaf2 100644\n--- a/hw/arm/fsl-imx8mm.c\n+++ b/hw/arm/fsl-imx8mm.c\n@@ -195,6 +195,11 @@ static void fsl_imx8mm_init(Object *obj)\n object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);\n }\n \n+ for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"spi%d\", i + 1);\n+ object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);\n+ }\n+\n object_initialize_child(obj, \"pcie\", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);\n object_initialize_child(obj, \"pcie_phy\", &s->pcie_phy,\n TYPE_FSL_IMX8M_PCIE_PHY);\n@@ -464,6 +469,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n qdev_get_gpio_in(gicdev, usdhc_table[i].irq));\n }\n \n+ /* ECSPIs */\n+ for (i = 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) {\n+ static const struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } spi_table[FSL_IMX8MM_NUM_ECSPIS] = {\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI1].addr, FSL_IMX8MM_ECSPI1_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI2].addr, FSL_IMX8MM_ECSPI2_IRQ },\n+ { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI3].addr, FSL_IMX8MM_ECSPI3_IRQ },\n+ };\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,\n+ qdev_get_gpio_in(gicdev, spi_table[i].irq));\n+ }\n+\n /* SNVS */\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {\n return;\n@@ -503,6 +528,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp)\n case FSL_IMX8MM_GIC_DIST:\n case FSL_IMX8MM_GIC_REDIST:\n case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5:\n+ case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3:\n case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4:\n case FSL_IMX8MM_PCIE1:\n case FSL_IMX8MM_PCIE_PHY1:\ndiff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h\nindex d6df16e9d4..13c044412a 100644\n--- a/include/hw/arm/fsl-imx8mm.h\n+++ b/include/hw/arm/fsl-imx8mm.h\n@@ -21,6 +21,7 @@\n #include \"hw/pci-host/designware.h\"\n #include \"hw/pci-host/fsl_imx8m_phy.h\"\n #include \"hw/sd/sdhci.h\"\n+#include \"hw/ssi/imx_spi.h\"\n #include \"qom/object.h\"\n #include \"qemu/units.h\"\n \n@@ -32,6 +33,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)\n \n enum FslImx8mmConfiguration {\n FSL_IMX8MM_NUM_CPUS = 4,\n+ FSL_IMX8MM_NUM_ECSPIS = 3,\n FSL_IMX8MM_NUM_GPIOS = 5,\n FSL_IMX8MM_NUM_I2CS = 4,\n FSL_IMX8MM_NUM_IRQS = 128,\n@@ -48,6 +50,7 @@ struct FslImx8mmState {\n IMX8MPCCMState ccm;\n IMX8MPAnalogState analog;\n IMX7SNVSState snvs;\n+ IMXSPIState spi[FSL_IMX8MM_NUM_ECSPIS];\n IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];\n IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];\n MemoryRegion ocram;\n@@ -177,6 +180,10 @@ enum FslImx8mmIrqs {\n FSL_IMX8MM_UART3_IRQ = 28,\n FSL_IMX8MM_UART4_IRQ = 29,\n \n+ FSL_IMX8MM_ECSPI1_IRQ = 31,\n+ FSL_IMX8MM_ECSPI2_IRQ = 32,\n+ FSL_IMX8MM_ECSPI3_IRQ = 33,\n+\n FSL_IMX8MM_I2C1_IRQ = 35,\n FSL_IMX8MM_I2C2_IRQ = 36,\n FSL_IMX8MM_I2C3_IRQ = 37,\n", "prefixes": [ "PATCHv6", "10/15" ] }