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GET /api/1.1/patches/2223208/?format=api
{ "id": 2223208, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223208/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-6@git.sr.ht/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<177618728515.4917.14466194789826252277-6@git.sr.ht>", "date": "2026-04-13T18:01:26", "name": "[qemu,v3,06/10] ot_uart: implement RX fifo and loopback", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2c331b15cb15641a67a4bce813f2aee4714eda44", "submitter": { "id": 92675, "url": "http://patchwork.ozlabs.org/api/1.1/people/92675/?format=api", "name": "~lexbaileylowrisc", "email": "lexbaileylowrisc@git.sr.ht" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-6@git.sr.ht/mbox/", "series": [ { "id": 499878, "url": "http://patchwork.ozlabs.org/api/1.1/series/499878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499878", "date": "2026-04-14T17:21:25", "name": "Update opentitan uart (part of supporting opentitan version 1)", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223208/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223208/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=G7p6Ue+L;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwB2D4wf4z1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 03:23:32 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wChSK-0005wA-LV; Tue, 14 Apr 2026 13:21:44 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <outgoing@sr.ht>)\n id 1wChSE-0005sX-9B; Tue, 14 Apr 2026 13:21:40 -0400", "from mail-a.sr.ht ([46.23.81.152])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <outgoing@sr.ht>)\n id 1wChSB-0007Kd-HC; Tue, 14 Apr 2026 13:21:37 -0400", "from git.sr.ht (unknown [46.23.81.155])\n by mail-a.sr.ht (Postfix) with ESMTPSA id 5BF7D20A3A;\n Tue, 14 Apr 2026 17:21:26 +0000 (UTC)" ], "DKIM-Signature": "a=rsa-sha256; bh=4eJ+HnMcX8p6InMQPVwB32zKkriVDrfCwoCMifz9Wxk=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1776187286; v=1;\n b=G7p6Ue+L+EiCXLw/Z2u42bGGayDw8T0AwqeYzg8a6Aj9FOJVxEWJVHcc5J+V0Ph3GP25TgzQ\n C+2uGzA4c2I8UcRWz+eu52QNhqoCnnWQih6NnDhT133hK7bMmdRLkA1dqPeJFvltPyCG/S87ORo\n rnvyEZQVaUEduhPbrL3gr9kkryYdn6ub94yWzM/pjKRHiOPRpCxuIUFDk5Dgw7ktt+cz6jzOWe6\n 2SZQKX4L97LDZs9E62t1tHJCuS3J/+lA+PPUUepUYGR8lls1W8+iiJU/OcE3lt8P15N+YjFX8l0\n GKpULKxRiXPRFdPxVhPNIUn+q1gF1/82yW8iWow1T6K+Q==", "From": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>", "Date": "Mon, 13 Apr 2026 19:01:26 +0100", "Subject": "[PATCH qemu v3 06/10] ot_uart: implement RX fifo and loopback", "Message-ID": "<177618728515.4917.14466194789826252277-6@git.sr.ht>", "X-Mailer": "git.sr.ht", "In-Reply-To": "<177618728515.4917.14466194789826252277-0@git.sr.ht>", "To": "qemu-riscv@nongnu.org, Alistair Francis <Alistair.Francis@wdc.com>", "Cc": "Paolo Bonzini <pbonzini@redhat.com>,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau <marcandre.lureau@redhat.com>,\n Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, qemu-devel@nongnu.org,\n qemu-riscv@nongnu.org, Amit Kumar-Hermosillo <amitkh@google.com>,\n nabihestefan <nabihestefan@google.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "Received-SPF": "pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht", "X-Spam_score_int": "-5", "X-Spam_score": "-0.6", "X-Spam_bar": "/", "X-Spam_report": "(-0.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_12_24=1.049,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-To": "~lexbaileylowrisc <lex.bailey@lowrisc.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Lex Bailey <lex.bailey@lowrisc.org>\n\nThe STATUS register value is now generated on every read instead of being\ntracked in memory since it has such a dynamic value. the receive fifo is now\nimplemented, and the system loopback mode. (line loopback is not supported)\n\nSigned-off-by: Lex Bailey <lex.bailey@lowrisc.org>\n---\n hw/char/ot_uart.c | 160 ++++++++++++++++++++++++++++++++--------------\n 1 file changed, 112 insertions(+), 48 deletions(-)", "diff": "diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex 2247db7110..3511a42fbe 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -140,6 +140,21 @@ static void ot_uart_update_irqs(OtUARTState *s)\n }\n }\n \n+static bool ot_uart_is_sys_loopack_enabled(const OtUARTState *s)\n+{\n+ return FIELD_EX32(s->regs[R_CTRL], CTRL, SLPBK);\n+}\n+\n+static bool ot_uart_is_tx_enabled(const OtUARTState *s)\n+{\n+ return FIELD_EX32(s->regs[R_CTRL], CTRL, TX);\n+}\n+\n+static bool ot_uart_is_rx_enabled(const OtUARTState *s)\n+{\n+ return FIELD_EX32(s->regs[R_CTRL], CTRL, RX);\n+}\n+\n static int ot_uart_can_receive(void *opaque)\n {\n OtUARTState *s = opaque;\n@@ -196,7 +211,7 @@ static void ot_uart_reset_rx_fifo(OtUARTState *s)\n fifo8_reset(&s->rx_fifo);\n s->regs[R_INTR_STATE] &= ~INTR_RX_WATERMARK_MASK;\n s->regs[R_INTR_STATE] &= ~INTR_RX_OVERFLOW_MASK;\n- if (FIELD_EX32(s->regs[R_CTRL], CTRL, RX)) {\n+ if (ot_uart_is_rx_enabled(s)) {\n qemu_chr_fe_accept_input(&s->chr);\n }\n }\n@@ -218,21 +233,37 @@ static void ot_uart_xmit(OtUARTState *s)\n return;\n }\n \n- /* instant drain the fifo when there's no back-end */\n- if (!qemu_chr_fe_backend_connected(&s->chr)) {\n- ot_uart_reset_tx_fifo(s);\n- ot_uart_update_irqs(s);\n- return;\n- }\n+ if (ot_uart_is_sys_loopack_enabled(s)) {\n+ /* system loopback mode, just forward to RX FIFO */\n+ uint32_t count = fifo8_num_used(&s->tx_fifo);\n+ buf = fifo8_pop_bufptr(&s->tx_fifo, count, &size);\n+ ot_uart_receive(s, buf, (int)size);\n+ count -= size;\n+ /*\n+ * there may be more data to send if data wraps around the end of TX\n+ * FIFO\n+ */\n+ if (count) {\n+ buf = fifo8_pop_bufptr(&s->tx_fifo, count, &size);\n+ ot_uart_receive(s, buf, (int)size);\n+ }\n+ } else {\n+ /* instant drain the fifo when there's no back-end */\n+ if (!qemu_chr_fe_backend_connected(&s->chr)) {\n+ ot_uart_reset_tx_fifo(s);\n+ ot_uart_update_irqs(s);\n+ return;\n+ }\n \n- /* get a continuous buffer from the FIFO */\n- buf =\n- fifo8_peek_bufptr(&s->tx_fifo, fifo8_num_used(&s->tx_fifo), &size);\n- /* send as much as possible */\n- ret = qemu_chr_fe_write(&s->chr, buf, (int)size);\n- /* if some characters where sent, remove them from the FIFO */\n- if (ret >= 0) {\n- fifo8_drop(&s->tx_fifo, ret);\n+ /* get a continuous buffer from the FIFO */\n+ buf =\n+ fifo8_peek_bufptr(&s->tx_fifo, fifo8_num_used(&s->tx_fifo), &size);\n+ /* send as much as possible */\n+ ret = qemu_chr_fe_write(&s->chr, buf, (int)size);\n+ /* if some characters where sent, remove them from the FIFO */\n+ if (ret >= 0) {\n+ fifo8_drop(&s->tx_fifo, ret);\n+ }\n }\n \n /* update INTR_STATE */\n@@ -269,7 +300,7 @@ static void uart_write_tx_fifo(OtUARTState *s, uint8_t val)\n s->tx_watermark_level = 0;\n }\n \n- if (FIELD_EX32(s->regs[R_CTRL], CTRL, TX)) {\n+ if (ot_uart_is_tx_enabled(s)) {\n ot_uart_xmit(s);\n }\n \n@@ -288,8 +319,6 @@ static void ot_uart_reset_enter(Object *obj, ResetType type)\n \n memset(&s->regs[0], 0, sizeof(s->regs));\n \n- s->regs[R_STATUS] = 0x0000003c;\n-\n s->tx_watermark_level = 0;\n for (unsigned index = 0; index < ARRAY_SIZE(s->irqs); index++) {\n qemu_set_irq(s->irqs[index], 0);\n@@ -305,6 +334,27 @@ static void ot_uart_reset_enter(Object *obj, ResetType type)\n ot_uart_update_irqs(s);\n }\n \n+static uint8_t ot_uart_read_rx_fifo(OtUARTState *s)\n+{\n+ uint8_t val;\n+\n+ if (!(s->regs[R_CTRL] & R_CTRL_RX_MASK)) {\n+ return 0;\n+ }\n+\n+ if (fifo8_is_empty(&s->rx_fifo)) {\n+ return 0;\n+ }\n+\n+ val = fifo8_pop(&s->rx_fifo);\n+\n+ if (ot_uart_is_rx_enabled(s) && !ot_uart_is_sys_loopack_enabled(s)) {\n+ qemu_chr_fe_accept_input(&s->chr);\n+ }\n+\n+ return val;\n+}\n+\n static uint64_t ot_uart_get_baud(OtUARTState *s)\n {\n uint64_t baud;\n@@ -327,32 +377,50 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n case R_INTR_ENABLE:\n case R_CTRL:\n case R_FIFO_CTRL:\n- case R_STATUS:\n retvalue = s->regs[reg];\n break;\n+ case R_STATUS:\n+ /* assume that UART always report RXIDLE */\n+ retvalue = R_STATUS_RXIDLE_MASK;\n+ /* report RXEMPTY or RXFULL */\n+ switch (fifo8_num_used(&s->rx_fifo)) {\n+ case 0:\n+ retvalue |= R_STATUS_RXEMPTY_MASK;\n+ break;\n+ case OT_UART_RX_FIFO_SIZE:\n+ retvalue |= R_STATUS_RXFULL_MASK;\n+ break;\n+ default:\n+ break;\n+ }\n+ /* report TXEMPTY+TXIDLE or TXFULL */\n+ switch (fifo8_num_used(&s->tx_fifo)) {\n+ case 0:\n+ retvalue |= R_STATUS_TXEMPTY_MASK | R_STATUS_TXIDLE_MASK;\n+ break;\n+ case OT_UART_TX_FIFO_SIZE:\n+ retvalue |= R_STATUS_TXFULL_MASK;\n+ break;\n+ default:\n+ break;\n+ }\n+ if (!ot_uart_is_tx_enabled(s)) {\n+ retvalue |= R_STATUS_TXIDLE_MASK;\n+ }\n+ if (!ot_uart_is_rx_enabled(s)) {\n+ retvalue |= R_STATUS_RXIDLE_MASK;\n+ }\n+ break;\n \n case R_RDATA:\n- retvalue = s->regs[R_RDATA];\n- if ((s->regs[R_CTRL] & R_CTRL_RX_MASK) && (s->rx_level > 0)) {\n- qemu_chr_fe_accept_input(&s->chr);\n-\n- s->rx_level -= 1;\n- s->regs[R_STATUS] &= ~R_STATUS_RXFULL_MASK;\n- if (s->rx_level == 0) {\n- s->regs[R_STATUS] |= R_STATUS_RXIDLE_MASK;\n- s->regs[R_STATUS] |= R_STATUS_RXEMPTY_MASK;\n- }\n- }\n+ retvalue = (uint32_t)ot_uart_read_rx_fifo(s);\n break;\n \n case R_FIFO_STATUS:\n- retvalue = s->regs[R_FIFO_STATUS];\n-\n- retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT;\n- retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT;\n-\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: RX fifos are not supported\\n\", __func__);\n+ retvalue =\n+ (fifo8_num_used(&s->rx_fifo) & 0xffu) << R_FIFO_STATUS_RXLVL_SHIFT;\n+ retvalue |=\n+ (fifo8_num_used(&s->tx_fifo) & 0xffu) << R_FIFO_STATUS_TXLVL_SHIFT;\n break;\n \n case R_VAL:\n@@ -416,10 +484,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n qemu_log_mask(LOG_UNIMP,\n \"%s: UART_CTRL_NF is not supported\\n\", __func__);\n }\n- if (value & R_CTRL_SLPBK_MASK) {\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: UART_CTRL_SLPBK is not supported\\n\", __func__);\n- }\n if (value & R_CTRL_LLPBK_MASK) {\n qemu_log_mask(LOG_UNIMP,\n \"%s: UART_CTRL_LLPBK is not supported\\n\", __func__);\n@@ -445,19 +509,19 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n }\n break;\n case R_WDATA:\n- uart_write_tx_fifo(s, value);\n+ uart_write_tx_fifo(s, (uint8_t)(value & R_WDATA_WDATA_MASK));\n break;\n \n case R_FIFO_CTRL:\n- s->regs[R_FIFO_CTRL] = value;\n-\n+ s->regs[R_FIFO_CTRL] =\n+ value & (R_FIFO_CTRL_RXILVL_MASK | R_FIFO_CTRL_TXILVL_MASK);\n if (value & R_FIFO_CTRL_RXRST_MASK) {\n- s->rx_level = 0;\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: RX fifos are not supported\\n\", __func__);\n+ ot_uart_reset_rx_fifo(s);\n+ ot_uart_update_irqs(s);\n }\n if (value & R_FIFO_CTRL_TXRST_MASK) {\n- s->tx_level = 0;\n+ ot_uart_reset_tx_fifo(s);\n+ ot_uart_update_irqs(s);\n }\n break;\n case R_OVRD:\n", "prefixes": [ "qemu", "v3", "06/10" ] }