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GET /api/1.1/patches/2223207/?format=api
{ "id": 2223207, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2223207/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-5@git.sr.ht/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<177618728515.4917.14466194789826252277-5@git.sr.ht>", "date": "2026-04-13T16:27:19", "name": "[qemu,v3,05/10] ot_uart: gather similar behaviours togeter in register read and write", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "22b9a5d8442de8df8bcf3fd7c228393cd1c5dc1c", "submitter": { "id": 92675, "url": "http://patchwork.ozlabs.org/api/1.1/people/92675/?format=api", "name": "~lexbaileylowrisc", "email": "lexbaileylowrisc@git.sr.ht" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/177618728515.4917.14466194789826252277-5@git.sr.ht/mbox/", "series": [ { "id": 499878, "url": "http://patchwork.ozlabs.org/api/1.1/series/499878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499878", "date": "2026-04-14T17:21:25", "name": "Update opentitan uart (part of supporting opentitan version 1)", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2223207/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223207/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=V8hSqag8;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fwB2C3JKqz1yHH\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 15 Apr 2026 03:23:31 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wChSK-0005va-7I; Tue, 14 Apr 2026 13:21:44 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <outgoing@sr.ht>)\n id 1wChSE-0005sV-8t; Tue, 14 Apr 2026 13:21:40 -0400", "from mail-a.sr.ht ([46.23.81.152])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <outgoing@sr.ht>)\n id 1wChSB-0007Kc-HL; Tue, 14 Apr 2026 13:21:37 -0400", "from git.sr.ht (unknown [46.23.81.155])\n by mail-a.sr.ht (Postfix) with ESMTPSA id 46FD920A39;\n Tue, 14 Apr 2026 17:21:26 +0000 (UTC)" ], "DKIM-Signature": "a=rsa-sha256; bh=bpoRrUp4pyhuvp+Q79o5fEv94I7SFuni9yO5BtCXukE=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1776187286; v=1;\n b=V8hSqag8a/UdhnMNak+X3IsUuqiWjVwl2E2Slf4oxj3SRa+FBY1JzRLIiOShtMdCev9Ia3Ku\n knlEHvL73PKlXlGLcmNsepUkjtpXRUreXp7AbyEr7/1W+bh/Rs31RoHP/t1jNf1eM4BB0gtaVAT\n QwWN/dwgp40LLQlqPHky4TqshQUmdYYsP6f50kHHOX2LDT+4qxdpxav9LQ52Vep/iq+yv8ki65Z\n EfPVbZu4gOD2N2Z4FS9Gx01EK/Eoz1uaGaPJbsR7OqARXCcoxlHOz5Y1xnSrYpF4CvOLfGzCB7Z\n 1nyxYfS4e2NS5QkovMJxX7KI2U4NCMpxud8/4e/UQZReQ==", "From": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>", "Date": "Mon, 13 Apr 2026 17:27:19 +0100", "Subject": "[PATCH qemu v3 05/10] ot_uart: gather similar behaviours togeter in\n register read and write", "Message-ID": "<177618728515.4917.14466194789826252277-5@git.sr.ht>", "X-Mailer": "git.sr.ht", "In-Reply-To": "<177618728515.4917.14466194789826252277-0@git.sr.ht>", "To": "qemu-riscv@nongnu.org, Alistair Francis <Alistair.Francis@wdc.com>", "Cc": "Paolo Bonzini <pbonzini@redhat.com>,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau <marcandre.lureau@redhat.com>,\n Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, qemu-devel@nongnu.org,\n qemu-riscv@nongnu.org, Amit Kumar-Hermosillo <amitkh@google.com>,\n nabihestefan <nabihestefan@google.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "Received-SPF": "pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht", "X-Spam_score_int": "-3", "X-Spam_score": "-0.4", "X-Spam_bar": "/", "X-Spam_report": "(-0.4 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_24_48=1.34,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-To": "~lexbaileylowrisc <lex.bailey@lowrisc.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Lex Bailey <lex.bailey@lowrisc.org>\n\nthe register read and write functions are each a large switch statement with\nmany similar behaviours in, this is mostly for enabling the use of specific\nregister names inside of log messages. this commit adds a lookup table for\nregister names and uses that instead, allowing much of the code in the register\nread and write functions to be deduplicated.\n\nthe write function was also missing a switch case for R_ALERT_TEST, so I added\nthat in this commit since it has a very simple implementation for now\n\nSigned-off-by: Lex Bailey <lex.bailey@lowrisc.org>\n---\n hw/char/ot_uart.c | 106 +++++++++++++++++++++++-----------------------\n 1 file changed, 53 insertions(+), 53 deletions(-)", "diff": "diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex f621fd3eae..2247db7110 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -99,9 +99,6 @@ REG32(TIMEOUT_CTRL, 0x30)\n R_CTRL_LLPBK_MASK | R_CTRL_PARITY_EN_MASK | R_CTRL_PARITY_ODD_MASK | \\\n R_CTRL_RXBLVL_MASK | R_CTRL_NCO_MASK)\n \n-#define CTRL_SUP_MASK \\\n- (R_CTRL_RX_MASK | R_CTRL_TX_MASK | R_CTRL_SLPBK_MASK | R_CTRL_NCO_MASK)\n-\n #define OT_UART_NCO_BITS 16\n #define OT_UART_TX_FIFO_SIZE 128\n #define OT_UART_RX_FIFO_SIZE 128\n@@ -112,6 +109,26 @@ REG32(TIMEOUT_CTRL, 0x30)\n #define R_LAST_REG (R_TIMEOUT_CTRL)\n #define REGS_COUNT (R_LAST_REG + 1u)\n #define REGS_SIZE (REGS_COUNT * sizeof(uint32_t))\n+#define REG_NAME(_reg_) \\\n+ ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : \"?\")\n+\n+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)\n+static const char *REG_NAMES[REGS_COUNT] = {\n+ REG_NAME_ENTRY(INTR_STATE),\n+ REG_NAME_ENTRY(INTR_ENABLE),\n+ REG_NAME_ENTRY(INTR_TEST),\n+ REG_NAME_ENTRY(ALERT_TEST),\n+ REG_NAME_ENTRY(CTRL),\n+ REG_NAME_ENTRY(STATUS),\n+ REG_NAME_ENTRY(RDATA),\n+ REG_NAME_ENTRY(WDATA),\n+ REG_NAME_ENTRY(FIFO_CTRL),\n+ REG_NAME_ENTRY(FIFO_STATUS),\n+ REG_NAME_ENTRY(OVRD),\n+ REG_NAME_ENTRY(VAL),\n+ REG_NAME_ENTRY(TIMEOUT_CTRL),\n+};\n+#undef REG_NAME_ENTRY\n \n static void ot_uart_update_irqs(OtUARTState *s)\n {\n@@ -304,23 +321,14 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n OtUARTState *s = opaque;\n uint64_t retvalue = 0;\n \n- switch (addr >> 2) {\n+ hwaddr reg = R32_OFF(addr);\n+ switch (reg) {\n case R_INTR_STATE:\n- retvalue = s->regs[R_INTR_STATE];\n- break;\n case R_INTR_ENABLE:\n- retvalue = s->regs[R_INTR_ENABLE];\n- break;\n- case R_INTR_TEST:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: wdata is write only\\n\", __func__);\n- break;\n-\n case R_CTRL:\n- retvalue = s->regs[R_CTRL];\n- break;\n+ case R_FIFO_CTRL:\n case R_STATUS:\n- retvalue = s->regs[R_STATUS];\n+ retvalue = s->regs[reg];\n break;\n \n case R_RDATA:\n@@ -336,14 +344,7 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n }\n }\n break;\n- case R_WDATA:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: wdata is write only\\n\", __func__);\n- break;\n \n- case R_FIFO_CTRL:\n- retvalue = s->regs[R_FIFO_CTRL];\n- break;\n case R_FIFO_STATUS:\n retvalue = s->regs[R_FIFO_STATUS];\n \n@@ -354,21 +355,21 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n \"%s: RX fifos are not supported\\n\", __func__);\n break;\n \n- case R_OVRD:\n- retvalue = s->regs[R_OVRD];\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: ovrd is not supported\\n\", __func__);\n- break;\n case R_VAL:\n- retvalue = s->regs[R_VAL];\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: val is not supported\\n\", __func__);\n- break;\n+ case R_OVRD:\n case R_TIMEOUT_CTRL:\n- retvalue = s->regs[R_TIMEOUT_CTRL];\n+ retvalue = s->regs[reg];\n qemu_log_mask(LOG_UNIMP,\n- \"%s: timeout_ctrl is not supported\\n\", __func__);\n+ \"%s: %s is not supported\\n\", __func__, REG_NAME(reg));\n+ break;\n+\n+ case R_ALERT_TEST:\n+ case R_INTR_TEST:\n+ case R_WDATA:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: %s is write only\\n\", __func__, REG_NAME(reg));\n break;\n+\n default:\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Bad offset 0x%\"HWADDR_PRIx\"\\n\", __func__, addr);\n@@ -384,7 +385,9 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n OtUARTState *s = opaque;\n uint32_t value = val64;\n \n- switch (addr >> 2) {\n+ hwaddr reg = R32_OFF(addr);\n+\n+ switch (reg) {\n case R_INTR_STATE:\n /* Write 1 clear */\n value &= INTR_MASK;\n@@ -401,7 +404,11 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n s->regs[R_INTR_STATE] |= value;\n ot_uart_update_irqs(s);\n break;\n-\n+ case R_ALERT_TEST:\n+ value &= R_ALERT_TEST_FATAL_FAULT_MASK;\n+ s->regs[reg] = value;\n+ /* This will also set an IRQ once the alert handler is added */\n+ break;\n case R_CTRL:\n s->regs[R_CTRL] = value;\n \n@@ -437,15 +444,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;\n }\n break;\n- case R_STATUS:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: status is read only\\n\", __func__);\n- break;\n-\n- case R_RDATA:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: rdata is read only\\n\", __func__);\n- break;\n case R_WDATA:\n uart_write_tx_fifo(s, value);\n break;\n@@ -462,10 +460,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n s->tx_level = 0;\n }\n break;\n- case R_FIFO_STATUS:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: fifo_status is read only\\n\", __func__);\n- break;\n case R_OVRD:\n if (value & R_OVRD_TXEN_MASK) {\n qemu_log_mask(LOG_UNIMP, \"%s: OVRD.TXEN is not supported\\n\",\n@@ -473,16 +467,22 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n }\n s->regs[R_OVRD] = value & R_OVRD_TXVAL_MASK;\n break;\n- case R_VAL:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: val is read only\\n\", __func__);\n- break;\n+\n case R_TIMEOUT_CTRL:\n s->regs[R_TIMEOUT_CTRL] =\n value & (R_TIMEOUT_CTRL_EN_MASK | R_TIMEOUT_CTRL_VAL_MASK);\n qemu_log_mask(LOG_UNIMP,\n \"%s: timeout_ctrl is not supported\\n\", __func__);\n break;\n+\n+ case R_STATUS:\n+ case R_RDATA:\n+ case R_FIFO_STATUS:\n+ case R_VAL:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: %s is read only\\n\", __func__, REG_NAME(reg));\n+ break;\n+\n default:\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Bad offset 0x%\"HWADDR_PRIx\"\\n\", __func__, addr);\n", "prefixes": [ "qemu", "v3", "05/10" ] }