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GET /api/1.1/patches/2222911/?format=api
{ "id": 2222911, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414005348.4767-5-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260414005348.4767-5-philmd@linaro.org>", "date": "2026-04-14T00:53:43", "name": "[v2,4/9] target/arm: Hoist MO_TE into MVE DO_VSTR() macro", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "06e601c9f5f299b9faab07e7b0ad3577a6f2f845", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.1/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260414005348.4767-5-philmd@linaro.org/mbox/", "series": [ { "id": 499764, "url": "http://patchwork.ozlabs.org/api/1.1/series/499764/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499764", "date": "2026-04-14T00:53:39", "name": "target/arm: Remove MO_TE to compile MVE/M helpers once", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499764/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222911/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222911/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Lxmb+Mye;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::330;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/mve_helper.c | 43 +++++++++++++++++--------------------\n 1 file changed, 20 insertions(+), 23 deletions(-)", "diff": "diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c\nindex fbb64889bf7..4bea0991de9 100644\n--- a/target/arm/tcg/mve_helper.c\n+++ b/target/arm/tcg/mve_helper.c\n@@ -235,7 +235,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \\\n+ mmu_idx); \\\n for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \\\n if (!(eci_mask & 1)) { \\\n continue; \\\n@@ -262,7 +263,8 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MFLAG | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MFLAG | MO_ALIGN, \\\n+ mmu_idx); \\\n for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE, eci_mask >>= ESIZE) { \\\n if (!(eci_mask & 1)) { \\\n continue; \\\n@@ -347,47 +349,42 @@ DO_VSTR(vstrh_w, MO_UW, 2, stw, 4, int32_t)\n \n DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD, false)\n DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrh_sg_sw, MO_TE | MO_SW, int16_t, ldw, 4,\n- int32_t, uint32_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrh_sg_sw, MO_SW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD, false)\n \n DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD, false)\n DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_ADD, false)\n DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrh_sg_uh, MO_TE | MO_UW, uint16_t, ldw, 2,\n- uint16_t, uint16_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrh_sg_uw, MO_TE | MO_UW, uint16_t, ldw, 4,\n- uint32_t, uint32_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrw_sg_uw, MO_TE | MO_UL, uint32_t, ldl, 4,\n- uint32_t, uint32_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrh_sg_uh, MO_UW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrh_sg_uw, MO_UW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrw_sg_uw, MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false)\n DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false)\n \n-DO_VLDR_SG(vldrh_sg_os_sw, MO_TE | MO_SW, int16_t, ldw, 4,\n+DO_VLDR_SG(vldrh_sg_os_sw, MO_SW, int16_t, ldw, 4,\n int32_t, uint32_t, ADDR_ADD_OSH, false)\n-DO_VLDR_SG(vldrh_sg_os_uh, MO_TE | MO_UW, uint16_t, ldw, 2,\n+DO_VLDR_SG(vldrh_sg_os_uh, MO_UW, uint16_t, ldw, 2,\n uint16_t, uint16_t, ADDR_ADD_OSH, false)\n-DO_VLDR_SG(vldrh_sg_os_uw, MO_TE | MO_UW, uint16_t, ldw, 4,\n+DO_VLDR_SG(vldrh_sg_os_uw, MO_UW, uint16_t, ldw, 4,\n uint32_t, uint32_t, ADDR_ADD_OSH, false)\n-DO_VLDR_SG(vldrw_sg_os_uw, MO_TE | MO_UL, uint32_t, ldl, 4,\n+DO_VLDR_SG(vldrw_sg_os_uw, MO_UL, uint32_t, ldl, 4,\n uint32_t, uint32_t, ADDR_ADD_OSW, false)\n DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false)\n \n DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false)\n DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false)\n DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false)\n-DO_VSTR_SG(vstrh_sg_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD, false)\n-DO_VSTR_SG(vstrh_sg_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD, false)\n-DO_VSTR_SG(vstrw_sg_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, false)\n+DO_VSTR_SG(vstrh_sg_uh, MO_UW, stw, 2, uint16_t, ADDR_ADD, false)\n+DO_VSTR_SG(vstrh_sg_uw, MO_UW, stw, 4, uint32_t, ADDR_ADD, false)\n+DO_VSTR_SG(vstrw_sg_uw, MO_UL, stl, 4, uint32_t, ADDR_ADD, false)\n DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false)\n \n-DO_VSTR_SG(vstrh_sg_os_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, false)\n-DO_VSTR_SG(vstrh_sg_os_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, false)\n-DO_VSTR_SG(vstrw_sg_os_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, false)\n+DO_VSTR_SG(vstrh_sg_os_uh, MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, false)\n+DO_VSTR_SG(vstrh_sg_os_uw, MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, false)\n+DO_VSTR_SG(vstrw_sg_os_uw, MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, false)\n DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false)\n \n-DO_VLDR_SG(vldrw_sg_wb_uw, MO_TE | MO_UL, uint32_t, ldl, 4,\n- uint32_t, uint32_t, ADDR_ADD, true)\n+DO_VLDR_SG(vldrw_sg_wb_uw, MO_UL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true)\n DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true)\n-DO_VSTR_SG(vstrw_sg_wb_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, true)\n+DO_VSTR_SG(vstrw_sg_wb_uw, MO_UL, stl, 4, uint32_t, ADDR_ADD, true)\n DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n \n /*\n", "prefixes": [ "v2", "4/9" ] }