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GET /api/1.1/patches/2222846/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2222846,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222846/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413205208.50643-9-mohamed@unpredictable.fr/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260413205208.50643-9-mohamed@unpredictable.fr>",
    "date": "2026-04-13T20:52:00",
    "name": "[v12,08/15] whpx: i386: kernel-irqchip=off fixes",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "43c129a3bf01c246b07be19f74fa0e2a66f092e5",
    "submitter": {
        "id": 91318,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/91318/?format=api",
        "name": "Mohamed Mediouni",
        "email": "mohamed@unpredictable.fr"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260413205208.50643-9-mohamed@unpredictable.fr/mbox/",
    "series": [
        {
            "id": 499753,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/499753/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499753",
            "date": "2026-04-13T20:51:52",
            "name": "whpx: i386: bug fixes, feature probing and CPUID",
            "version": 12,
            "mbox": "http://patchwork.ozlabs.org/series/499753/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2222846/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2222846/checks/",
    "tags": {},
    "headers": {
        "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>",
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        ],
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        "mail-alias-created-date": "1752046281608",
        "From": "Mohamed Mediouni <mohamed@unpredictable.fr>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "Phil Dennis-Jordan <phil@philjordan.eu>,\n Pedro Barbuda <pbarbuda@microsoft.com>,\n \"Michael S. Tsirkin\" <mst@redhat.com>, Wei Liu <wei.liu@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>, Roman Bolshakov <rbolshakov@ddn.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>, Zhao Liu <zhao1.liu@intel.com>",
        "Subject": "[PATCH v12 08/15] whpx: i386: kernel-irqchip=off fixes",
        "Date": "Mon, 13 Apr 2026 22:52:00 +0200",
        "Message-ID": "<20260413205208.50643-9-mohamed@unpredictable.fr>",
        "X-Mailer": "git-send-email 2.50.1",
        "In-Reply-To": "<20260413205208.50643-1-mohamed@unpredictable.fr>",
        "References": "<20260413205208.50643-1-mohamed@unpredictable.fr>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-Proofpoint-GUID": "-AoHmE8lNTu1OBS9NuBWbcAipxXXwB-N",
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        "X-Spam_bar": "--",
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        "List-Id": "qemu development <qemu-devel.nongnu.org>",
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    },
    "content": "This was really... quite broken. After fixing this,\nWindows boots with kernel-irqchip=off.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n include/system/whpx-common.h |  1 +\n target/i386/whpx/whpx-all.c  | 43 +++++-------------------------------\n 2 files changed, 7 insertions(+), 37 deletions(-)",
    "diff": "diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h\nindex 04289afd97..3406c20fec 100644\n--- a/include/system/whpx-common.h\n+++ b/include/system/whpx-common.h\n@@ -4,6 +4,7 @@\n \n struct AccelCPUState {\n     bool window_registered;\n+    int window_priority;\n     bool interruptable;\n     bool ready_for_pic_interrupt;\n     uint64_t tpr;\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 9827c93df1..62542922a4 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -22,6 +22,8 @@\n #include \"qemu/main-loop.h\"\n #include \"hw/core/boards.h\"\n #include \"hw/intc/ioapic.h\"\n+#include \"hw/intc/i8259.h\"\n+#include \"hw/i386/x86.h\"\n #include \"hw/i386/apic_internal.h\"\n #include \"qemu/error-report.h\"\n #include \"qapi/error.h\"\n@@ -371,28 +373,6 @@ static int whpx_set_tsc(CPUState *cpu)\n     return 0;\n }\n \n-/*\n- * The CR8 register in the CPU is mapped to the TPR register of the APIC,\n- * however, they use a slightly different encoding. Specifically:\n- *\n- *     APIC.TPR[bits 7:4] = CR8[bits 3:0]\n- *\n- * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64\n- * and IA-32 Architectures Software Developer's Manual.\n- *\n- * The functions below translate the value of CR8 to TPR and vice versa.\n- */\n-\n-static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)\n-{\n-    return tpr >> 4;\n-}\n-\n-static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)\n-{\n-    return cr8 << 4;\n-}\n-\n void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n {\n     struct whpx_state *whpx = &whpx_global;\n@@ -421,7 +401,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n     v86 = (env->eflags & VM_MASK);\n     r86 = !(env->cr[0] & CR0_PE_MASK);\n \n-    vcpu->tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+    vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n     vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n     idx = 0;\n@@ -692,17 +672,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n                      hr);\n     }\n \n-    if (whpx_irqchip_in_kernel()) {\n-        /*\n-         * Fetch the TPR value from the emulated APIC. It may get overwritten\n-         * below with the value from CR8 returned by\n-         * WHvGetVirtualProcessorRegisters().\n-         */\n-        whpx_apic_get(x86_cpu->apic_state);\n-        vcpu->tpr = whpx_apic_tpr_to_cr8(\n-            cpu_get_apic_tpr(x86_cpu->apic_state));\n-    }\n-\n     idx = 0;\n \n     /* Indexes for first 16 registers match between HV and QEMU definitions */\n@@ -751,7 +720,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n     tpr = vcxt.values[idx++].Reg64;\n     if (tpr != vcpu->tpr) {\n         vcpu->tpr = tpr;\n-        cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));\n+        cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n     }\n \n     /* 8 Debug Registers - Skipped */\n@@ -1690,7 +1659,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n      }\n \n     /* Sync the TPR to the CR8 if was modified during the intercept */\n-    tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+    tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n     if (tpr != vcpu->tpr) {\n         vcpu->tpr = tpr;\n         reg_values[reg_count].Reg64 = tpr;\n@@ -1737,7 +1706,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n     if (vcpu->tpr != tpr) {\n         vcpu->tpr = tpr;\n         bql_lock();\n-        cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));\n+        cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n         bql_unlock();\n     }\n \n",
    "prefixes": [
        "v12",
        "08/15"
    ]
}