Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2222596/?format=api
{ "id": 2222596, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222596/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260413071401.1151-2-jian.yang@mediatek.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260413071401.1151-2-jian.yang@mediatek.com>", "date": "2026-04-13T07:13:55", "name": "[1/2] PCI: mediatek-gen3: Fix PERST# control timing during system startup", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8a448594269d851921bdd238e3907c577dacded3", "submitter": { "id": 85572, "url": "http://patchwork.ozlabs.org/api/1.1/people/85572/?format=api", "name": "Jian Yang", "email": "jian.yang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260413071401.1151-2-jian.yang@mediatek.com/mbox/", "series": [ { "id": 499653, "url": "http://patchwork.ozlabs.org/api/1.1/series/499653/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499653", "date": "2026-04-13T07:13:55", "name": "PCI: mediatek-gen3: Fix the control timing of PERST#", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499653/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222596/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222596/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52415-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256\n header.s=dk header.b=cx3+SzkQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-52415-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com\n header.b=\"cx3+SzkQ\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=60.244.123.138", "smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=mediatek.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=mediatek.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvJYp2Q6Sz1yDF\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 13 Apr 2026 17:14:22 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 071D93004068\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 13 Apr 2026 07:14:20 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id BEBE1392802;\n\tMon, 13 Apr 2026 07:14:17 +0000 (UTC)", "from mailgw01.mediatek.com (unknown [60.244.123.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id A67B9392C28;\n\tMon, 13 Apr 2026 07:14:15 +0000 (UTC)", "from mtkmbs09n1.mediatek.inc [(172.21.101.35)] by\n mailgw01.mediatek.com\n\t(envelope-from <jian.yang@mediatek.com>)\n\t(Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256)\n\twith ESMTP id 608280731; Mon, 13 Apr 2026 15:14:10 +0800", "from mtkmbs11n1.mediatek.inc (172.21.101.185) by\n MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.2562.29; Mon, 13 Apr 2026 15:14:09 +0800", "from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by\n mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id\n 15.2.2562.29 via Frontend Transport; Mon, 13 Apr 2026 15:14:08 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776064457; cv=none;\n b=jTgAi9CRTbXB/K8eBlErirtl3ZkavBGrascqyRoKf2NO3//pwikg2tKMcYkvHj3ZdrDSNqGzxvggWAViQK49/iHcAITFtyZwnCB0aam2TeBcZrjKZxIQLrz85F8QblXa3wHFGKbbf//Xi7xN9jy9FDZFmJUoS2gNl+GW2J9fhIA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776064457; c=relaxed/simple;\n\tbh=3EjBwo8siPsKWZlBsiISooyIR23JHiOwTQIO2hrgy5o=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=dP6kne83uY9FOOPsV7CD1j0XWNHlCy9k22qiPmopoW0GXaSaHx2GV3fVTFoEzfOdCdKGW910Ke2c8B/MKbMobyna+3ufMSL44mlffQxGqLspE0fNC/Hj/iren52ykn9JNkWylFOQCblAvYb8qdCVkKdmZze+xKrSm9ZgLpVF+Ic=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=mediatek.com;\n spf=pass smtp.mailfrom=mediatek.com;\n dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com\n header.b=cx3+SzkQ; arc=none smtp.client-ip=60.244.123.138", "X-UUID": [ "5df03d42370811f1ae70033691e9ac7d-20260413", "5df03d42370811f1ae70033691e9ac7d-20260413" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=mediatek.com; s=dk;\n\th=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;\n bh=we87XqmmyOUTzDF+stAxamWC1PGZ1tSA3Wr3kTUnazg=;\n\tb=cx3+SzkQLq9Vcl74SFReYnSJwFdftXWqA7UCK+lRedFBROkEfCz0++R3dZDlzfODKL1XehlgOjQ4ot4aafjKVxQopE/iGdFauKLPT8vHpoPQ0QSy18TOuxLgqcUCcLWT50K/6mh9PRi+jPoS1SZ1uLP9IbEzyt2Fhbvpq/V7jqM=;", "X-CID-P-RULE": "Release_Ham", "X-CID-O-INFO": "VERSION:1.3.12,REQID:53e0379f-17c6-40c5-8711-5a915eb6763a,IP:0,U\n\tRL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO\n\tN:release,TS:-25", "X-CID-META": "VersionHash:e7bac3a,CLOUDID:5654de94-f8ef-4ca8-bea0-143568f9ca1d,B\n\tulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont\n\tent:0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0\n\t,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0", "X-CID-BVR": "2,SSN|SDN", "X-CID-BAS": "2,SSN|SDN,0,_", "X-CID-FACTOR": "TF_CID_SPAM_SNR", "X-CID-RHF": "D41D8CD98F00B204E9800998ECF8427E", "From": "Jian Yang <jian.yang@mediatek.com>", "To": "Matthias Brugger <matthias.bgg@gmail.com>,\n AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,\n Ryder Lee <ryder.lee@mediatek.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>,\n\t<Project_Global_Chrome_Upstream_Group@mediatek.com>,\n\t<jian.yang@mediatek.com>, <chuanjia.liu@mediatek.com>,\n\t<yonglong.wu@mediatek.com>", "Subject": "[PATCH 1/2] PCI: mediatek-gen3: Fix PERST# control timing during\n system startup", "Date": "Mon, 13 Apr 2026 15:13:55 +0800", "Message-ID": "<20260413071401.1151-2-jian.yang@mediatek.com>", "X-Mailer": "git-send-email 2.46.0", "In-Reply-To": "<20260413071401.1151-1-jian.yang@mediatek.com>", "References": "<20260413071401.1151-1-jian.yang@mediatek.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain" }, "content": "Some of MediaTek's chip will stop generating REFCLK if the\nPCIE_PHY_RSTB signal of PCIe controller is asserted.\n\nWe have to adjust the control timing as follows to ensure that PERST#\nwill be de-asserted after the REFCLK is stable:\nAssert all reset signals -> delay 10ms -> De-assert all reset signals\nexcept PERST# -> delay 100ms -> De-assert PERST#\n\nSigned-off-by: Jian Yang <jian.yang@mediatek.com>\n---\n drivers/pci/controller/pcie-mediatek-gen3.c | 25 ++++++++++++++++++---\n 1 file changed, 22 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c\nindex b0accd828589..58ba1aa35a22 100644\n--- a/drivers/pci/controller/pcie-mediatek-gen3.c\n+++ b/drivers/pci/controller/pcie-mediatek-gen3.c\n@@ -62,6 +62,11 @@\n #define PCIE_PHY_RSTB\t\t\tBIT(1)\n #define PCIE_BRG_RSTB\t\t\tBIT(2)\n #define PCIE_PE_RSTB\t\t\tBIT(3)\n+/*\n+ * Described in the datasheet of MediaTek PCIe Gen3 controller.\n+ * After set PCIE_BRG_RSTB, wait 10ms before accessing PCIe internal registers.\n+ */\n+#define PCIE_BRG_RST_RDY_MS\t\t10\n \n #define PCIE_LTSSM_STATUS_REG\t\t0x150\n #define PCIE_LTSSM_STATE_MASK\t\tGENMASK(28, 24)\n@@ -430,6 +435,21 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)\n \t\treturn err;\n \t}\n \n+\t/*\n+\t * Some of MediaTek's chips won't output REFCLK when PCIE_PHY_RSTB is\n+\t * asserted, we have to de-assert MAC & PHY & BRG reset signals first\n+\t * to allow the REFCLK to be stable. While PCIE_BRG_RSTB is asserted,\n+\t * there is a short period during which the PCIe internal register\n+\t * cannot be accessed, so we need to wait 10ms here.\n+\t */\n+\tmsleep(PCIE_BRG_RST_RDY_MS);\n+\n+\tif (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {\n+\t\t/* De-assert MAC, PHY and BRG reset signals */\n+\t\tval &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);\n+\t\twritel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);\n+\t}\n+\n \t/*\n \t * Described in PCIe CEM specification revision 6.0.\n \t *\n@@ -439,9 +459,8 @@ static int mtk_pcie_devices_power_up(struct mtk_gen3_pcie *pcie)\n \tmsleep(PCIE_T_PVPERL_MS);\n \n \tif (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {\n-\t\t/* De-assert reset signals */\n-\t\tval &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB |\n-\t\t\t PCIE_PE_RSTB);\n+\t\t/* De-assert PERST# signal */\n+\t\tval &= ~PCIE_PE_RSTB;\n \t\twritel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);\n \t}\n \n", "prefixes": [ "1/2" ] }