Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2222474/?format=api
{ "id": 2222474, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222474/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/c2838d2c9fc0135bf346ee3754d5e519157bab9d.1775959096.git.chao.liu.zevorn@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<c2838d2c9fc0135bf346ee3754d5e519157bab9d.1775959096.git.chao.liu.zevorn@gmail.com>", "date": "2026-04-12T02:20:24", "name": "[v6,7/7] target/riscv: add sdtrig trigger action=debug mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a017f6d188b67c81ae0a3c5ea97f2042803007ef", "submitter": { "id": 92265, "url": "http://patchwork.ozlabs.org/api/1.1/people/92265/?format=api", "name": "Chao Liu", "email": "chao.liu.zevorn@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/c2838d2c9fc0135bf346ee3754d5e519157bab9d.1775959096.git.chao.liu.zevorn@gmail.com/mbox/", "series": [ { "id": 499584, "url": "http://patchwork.ozlabs.org/api/1.1/series/499584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584", "date": "2026-04-12T02:20:20", "name": "riscv: add initial sdext support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222474/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222474/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=CjSdkGAu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4ftZ7h6phHz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Sun, 12 Apr 2026 12:22:40 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wBkSG-0004Jp-2a; Sat, 11 Apr 2026 22:21:44 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <chao.liu.zevorn@gmail.com>)\n id 1wBkSF-0004JU-8H\n for qemu-devel@nongnu.org; Sat, 11 Apr 2026 22:21:43 -0400", "from mail-qv1-xf42.google.com ([2607:f8b0:4864:20::f42])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <chao.liu.zevorn@gmail.com>)\n id 1wBkSD-0000ca-F9\n for qemu-devel@nongnu.org; Sat, 11 Apr 2026 22:21:43 -0400", "by mail-qv1-xf42.google.com with SMTP id\n 6a1803df08f44-8a3b0242631so39291466d6.3\n for <qemu-devel@nongnu.org>; Sat, 11 Apr 2026 19:21:41 -0700 (PDT)", "from ZEVORN-PC.bbrouter ([162.244.208.119])\n by smtp.gmail.com with ESMTPSA id\n 6a1803df08f44-8aca05592ecsm15455576d6.29.2026.04.11.19.21.35\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 11 Apr 2026 19:21:40 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1775960500; x=1776565300; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=vazYcj8GwpUqusYCDniEwJxYizenODa1Oa0Jn+0NlQQ=;\n b=CjSdkGAuncLKJ+k1frGeTMPQool1+ZXS8zYT8H+3OeLocYGo12jELlCWE+YNbhu/dU\n zEkMtTORNfJNemfyqDq+MqW9DGI28U6CQ/63NRKoFl8YJU0n3HrUbXqfKmKYzEWkCGUR\n 8UUDKQifSxuNoLaQRtHxDRf8v1qeKFod6dglUKHBVR6bJ8lQ8IfaQ8WsVQfex+/yJMH7\n x+HiS3EFPjixDB9xMz0Ss+qJU8frvqgI1+ojfoM+a3Bm6IhEjYglXdMfnAQ6iQ693uRD\n g7Zdox2DvrQMEsm1lzmccZUQvdxpx0Nugj9PpbWELkk0ZmODLeilSkyE0fKvdgeixejx\n P/dQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775960500; x=1776565300;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=vazYcj8GwpUqusYCDniEwJxYizenODa1Oa0Jn+0NlQQ=;\n b=eoz9//NXU29s6DrTRqyXUz82n1HLVOKB8tlNaChqrovleq725DTa9ZScmZCgWCP5EY\n mn2dnD95JOTusdC4A/a97t68EADHzBdIJpFXaOga9CudbSzr6DVO0PMRVWqv+1afQBFV\n FYUgZGTKCI3RQGiQFJOW0BPPh6odLxRYW+MRfq6lSXx0rYzbywiJKU4COhDEeNNrEsO3\n 1ZIk3w6IOncWqD0lPSW15EImn/C23FTdP5CsCuRjlA5uXTY1T/ntIEr5umLkM1bVtcb6\n KwdJGyo2dHIU49vQOpWNXUPmNvJJAiYP/YFKg8+vxU1bhTHtw5T/1BMa+lO7AqdWPMoB\n 9VMQ==", "X-Gm-Message-State": "AOJu0YyZJT3MB6jye6wsuvXuyAc/OT/Tk2PFvz/q2+2BnI5Y1bOGjBUE\n jDwacfh1je++nvhTdJN2qeRSdX2tYXOA1Coko/2N/TgchQSehHvrtSTw", "X-Gm-Gg": "AeBDiesRQZidFsxrGfWJJ4iYp2Cgl6eFmd+1plMBWsiVHOR/6U+qx0OPOBrhP5Iafbu\n wY35YBJ2NG2PsksOB93APSeqn9ldxpsVJWIkct2NRWS2OF6QsZxYIyzJ4frsiYoU/2rr4FkQYoz\n dfWULtmnc6AZe5cHEXtggxPHEIkqdzfEl2n9nTUASVr2uis6dRNhL8sxXgCvsoy0eGXrig+6ZmO\n mQTyK4pS312bOVvnwiv3tXOyLibXmBUo/mBJbY0bShLk3TQZAJrfjE6OQIa4uHnXMPc9R/eC1X5\n aDpv2SB3Khj0/VN56W1SAe/LPrUZmji9JV3ULksf1vxZrpALErI+u93YlR9OSLuK0502b+p6Pl0\n XgKIwviP4UJl66oMO+ICxvZOMAxUjMM5lS6oX3OZyXsXSRPzURYvx6MIXLJ2p4cLNgc1XkKoI99\n DaxUbVsnNyZIsocv7gD+9JK5Q63ZXVbHPcs40NzETMXRB3Dq3Cg03lI1L5I1GSK71blrfM", "X-Received": "by 2002:a05:622a:4009:b0:50d:ce35:6e67 with SMTP id\n d75a77b69052e-50dd5ba3bd7mr124645941cf.42.1775960500394;\n Sat, 11 Apr 2026 19:21:40 -0700 (PDT)", "From": "Chao Liu <chao.liu.zevorn@gmail.com>", "To": "Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>,\n Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>", "Cc": "qemu-devel@nongnu.org, tangtao1634@phytium.com.cn,\n devel@lists.libvirt.org,\n qemu-riscv@nongnu.org", "Subject": "[PATCH v6 7/7] target/riscv: add sdtrig trigger action=debug mode", "Date": "Sun, 12 Apr 2026 10:20:24 +0800", "Message-ID": "\n <c2838d2c9fc0135bf346ee3754d5e519157bab9d.1775959096.git.chao.liu.zevorn@gmail.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<cover.1775959096.git.chao.liu.zevorn@gmail.com>", "References": "<cover.1775959096.git.chao.liu.zevorn@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::f42;\n envelope-from=chao.liu.zevorn@gmail.com; helo=mail-qv1-xf42.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "RISC-V Debug Specification:\nhttps://github.com/riscv/riscv-debug-spec/releases/tag/1.0\n\nAllow mcontrol/mcontrol6 action=1 when Sdext is enabled. When such a\ntrigger hits, enter Debug Mode with cause=trigger and stop with\nEXCP_DEBUG.\n\nAlso report inst-count triggers in tinfo and read their action field.\n\nSigned-off-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nTested-by: Tao Tang <tangtao1634@phytium.com.cn>\n---\n target/riscv/debug.c | 53 ++++++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 51 insertions(+), 2 deletions(-)", "diff": "diff --git a/target/riscv/debug.c b/target/riscv/debug.c\nindex 5877a60c50..6c69c2f796 100644\n--- a/target/riscv/debug.c\n+++ b/target/riscv/debug.c\n@@ -110,6 +110,8 @@ static trigger_action_t get_trigger_action(CPURISCVState *env,\n action = (tdata1 & TYPE6_ACTION) >> 12;\n break;\n case TRIGGER_TYPE_INST_CNT:\n+ action = tdata1 & ITRIGGER_ACTION;\n+ break;\n case TRIGGER_TYPE_INT:\n case TRIGGER_TYPE_EXCP:\n case TRIGGER_TYPE_EXT_SRC:\n@@ -280,6 +282,7 @@ static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3)\n \n static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)\n {\n+ CPUState *cs = env_cpu(env);\n trigger_action_t action = get_trigger_action(env, trigger_index);\n \n switch (action) {\n@@ -289,6 +292,21 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)\n riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);\n break;\n case DBG_ACTION_DBG_MODE:\n+ if (!env_archcpu(env)->cfg.ext_sdext) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"trigger action=debug mode requires Sdext\\n\");\n+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);\n+ }\n+ riscv_cpu_enter_debug_mode(env, env->pc, DCSR_CAUSE_TRIGGER);\n+ /*\n+ * If this came from the Trigger Module's CPU breakpoint/watchpoint,\n+ * we're already returning via EXCP_DEBUG. Otherwise, stop now.\n+ */\n+ if (cs->exception_index != EXCP_DEBUG) {\n+ cs->exception_index = EXCP_DEBUG;\n+ cpu_loop_exit_restore(cs, GETPC());\n+ }\n+ break;\n case DBG_ACTION_TRACE0:\n case DBG_ACTION_TRACE1:\n case DBG_ACTION_TRACE2:\n@@ -441,6 +459,7 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,\n {\n target_ulong val;\n uint32_t size;\n+ uint32_t action;\n \n /* validate the generic part first */\n val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH);\n@@ -448,11 +467,25 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,\n /* validate unimplemented (always zero) bits */\n warn_always_zero_bit(ctrl, TYPE2_MATCH, \"match\");\n warn_always_zero_bit(ctrl, TYPE2_CHAIN, \"chain\");\n- warn_always_zero_bit(ctrl, TYPE2_ACTION, \"action\");\n warn_always_zero_bit(ctrl, TYPE2_TIMING, \"timing\");\n warn_always_zero_bit(ctrl, TYPE2_SELECT, \"select\");\n warn_always_zero_bit(ctrl, TYPE2_HIT, \"hit\");\n \n+ action = (ctrl & TYPE2_ACTION) >> 12;\n+ if (action == DBG_ACTION_BP) {\n+ val |= ctrl & TYPE2_ACTION;\n+ } else if (action == DBG_ACTION_DBG_MODE) {\n+ if (env_archcpu(env)->cfg.ext_sdext) {\n+ val |= ctrl & TYPE2_ACTION;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"trigger action=debug mode requires Sdext\\n\");\n+ }\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"trigger action: %u is not supported\\n\",\n+ action);\n+ }\n+\n /* validate size encoding */\n size = type2_breakpoint_size(env, ctrl);\n if (access_size[size] == -1) {\n@@ -569,6 +602,7 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,\n {\n target_ulong val;\n uint32_t size;\n+ uint32_t action;\n \n /* validate the generic part first */\n val = tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH6);\n@@ -576,11 +610,25 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,\n /* validate unimplemented (always zero) bits */\n warn_always_zero_bit(ctrl, TYPE6_MATCH, \"match\");\n warn_always_zero_bit(ctrl, TYPE6_CHAIN, \"chain\");\n- warn_always_zero_bit(ctrl, TYPE6_ACTION, \"action\");\n warn_always_zero_bit(ctrl, TYPE6_TIMING, \"timing\");\n warn_always_zero_bit(ctrl, TYPE6_SELECT, \"select\");\n warn_always_zero_bit(ctrl, TYPE6_HIT, \"hit\");\n \n+ action = (ctrl & TYPE6_ACTION) >> 12;\n+ if (action == DBG_ACTION_BP) {\n+ val |= ctrl & TYPE6_ACTION;\n+ } else if (action == DBG_ACTION_DBG_MODE) {\n+ if (env_archcpu(env)->cfg.ext_sdext) {\n+ val |= ctrl & TYPE6_ACTION;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"trigger action=debug mode requires Sdext\\n\");\n+ }\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"trigger action: %u is not supported\\n\",\n+ action);\n+ }\n+\n /* validate size encoding */\n size = extract32(ctrl, 16, 4);\n if (access_size[size] == -1) {\n@@ -919,6 +967,7 @@ target_ulong tinfo_csr_read(CPURISCVState *env)\n {\n /* assume all triggers support the same types of triggers */\n return BIT(TRIGGER_TYPE_AD_MATCH) |\n+ BIT(TRIGGER_TYPE_INST_CNT) |\n BIT(TRIGGER_TYPE_AD_MATCH6);\n }\n \n", "prefixes": [ "v6", "7/7" ] }