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GET /api/1.1/patches/2222473/?format=api
{ "id": 2222473, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222473/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/99f0437cbb0169ffa318af4864ee48af22abeb17.1775959096.git.chao.liu.zevorn@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<99f0437cbb0169ffa318af4864ee48af22abeb17.1775959096.git.chao.liu.zevorn@gmail.com>", "date": "2026-04-12T02:20:18", "name": "[v6,1/7] target/riscv: deprecate 'debug' CPU property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "da14e307200c4bb99f5f1284659275724c6d4a8c", "submitter": { "id": 92265, "url": "http://patchwork.ozlabs.org/api/1.1/people/92265/?format=api", "name": "Chao Liu", "email": "chao.liu.zevorn@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/99f0437cbb0169ffa318af4864ee48af22abeb17.1775959096.git.chao.liu.zevorn@gmail.com/mbox/", "series": [ { "id": 499584, "url": "http://patchwork.ozlabs.org/api/1.1/series/499584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499584", "date": "2026-04-12T02:20:20", "name": "riscv: add initial sdext support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222473/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222473/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=tGR+cNui;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-qv1-xf43.google.com", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1,\n FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\n\nStarting on commit f31ba686a9 (\"target/riscv/cpu.c: add 'sdtrig' in\nriscv,isa') the 'debug' flag has been used as an alias for 'sdtrig'.\n\nWe're going to add more debug trigger extensions, e.g. 'sdext' [1]. And\nall of a sudden the existence of this flag is now weird. Do we keep it\nas a 'sdtrig' only or do we add 'sdext'?\n\nThe solution proposed here is to deprecate it. The flag was introduced a\nlong time ago as a way to encapsulate support for all debug related\nCSRs. Today we have specific debug trigger extensions and there's no\nmore use for a generic 'debug' flag. Users should be encouraged to\nenable/disable extensions directly instead of using \"made-up\" flags that\nexists only in a QEMU context.\n\nThe following changes are made:\n\n- 'ext_sdtrig' flag was added in cpu->cfg. 'debug' flag was removed from\n cpu->cfg;\n- All occurrences of cpu->cfg.debug were replaced to 'ext_sdtrig';\n- Two explicit getters and setters for the 'debug' property were added.\n The property will simply get/set ext_sdtrig;\n- vmstate_debug was renamed to vmstate_sdtrig. We're aware that this\n will impact migration between QEMU 10.2 to newer versions, but we're\n still in a point where the migration break cost isn't big enough to\n justify adding migration compatibility scaffolding.\n\nFinally, deprecated.rst was updated to deprecate 'debug' and encourage\nusers to use 'ext_sdtrig' instead.\n\n[1] https://lore.kernel.org/qemu-devel/cover.1768622881.git.chao.liu.zevorn@gmail.com/\n\nSigned-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nTested-by: Tao Tang <tangtao1634@phytium.com.cn>\n---\n docs/about/deprecated.rst | 7 +++++\n target/riscv/cpu.c | 51 ++++++++++++++++++++++++++++---\n target/riscv/cpu_cfg_fields.h.inc | 2 +-\n target/riscv/csr.c | 2 +-\n target/riscv/machine.c | 24 +++++++--------\n target/riscv/tcg/tcg-cpu.c | 2 +-\n 6 files changed, 69 insertions(+), 19 deletions(-)", "diff": "diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst\nindex a6d6a71326..cba050334b 100644\n--- a/docs/about/deprecated.rst\n+++ b/docs/about/deprecated.rst\n@@ -452,6 +452,13 @@ It was implemented as a no-op instruction in TCG up to QEMU 9.0, but\n only with ``-cpu max`` (which does not guarantee migration compatibility\n across versions).\n \n+``debug=true|false`` on RISC-V CPUs (since 11.0)\n+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\n+\n+This option, since QEMU 10.1, has been a simple alias to the ``sdtrig``\n+extension. Users are advised to enable/disable ``sdtrig`` directly instead\n+of using ``debug``.\n+\n Backwards compatibility\n -----------------------\n \ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 38286b6b40..6208201538 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -210,7 +210,7 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),\n ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),\n ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),\n- ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),\n+ ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig),\n ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),\n ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),\n ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),\n@@ -783,7 +783,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)\n env->vill = true;\n \n #ifndef CONFIG_USER_ONLY\n- if (cpu->cfg.debug) {\n+ if (cpu->cfg.ext_sdtrig) {\n riscv_trigger_reset_hold(env);\n }\n \n@@ -947,7 +947,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)\n riscv_cpu_register_gdb_regs_for_features(cs);\n \n #ifndef CONFIG_USER_ONLY\n- if (cpu->cfg.debug) {\n+ if (cpu->cfg.ext_sdtrig) {\n riscv_trigger_realize(&cpu->env);\n }\n #endif\n@@ -1126,6 +1126,14 @@ static void riscv_cpu_init(Object *obj)\n cpu->env.vext_ver = VEXT_VERSION_1_00_0;\n cpu->cfg.max_satp_mode = -1;\n \n+ /*\n+ * 'debug' started being deprecated in 11.0, been just a proxy\n+ * to set ext_sdtrig ever since. It has been enabled by default\n+ * for a long time though, so we're stuck with setting set 'strig'\n+ * by default too. At least for now ...\n+ */\n+ cpu->cfg.ext_sdtrig = true;\n+\n if (mcc->def->profile) {\n mcc->def->profile->enabled = true;\n }\n@@ -1240,6 +1248,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {\n MULTI_EXT_CFG_BOOL(\"smcdeleg\", ext_smcdeleg, false),\n MULTI_EXT_CFG_BOOL(\"sscsrind\", ext_sscsrind, false),\n MULTI_EXT_CFG_BOOL(\"ssccfg\", ext_ssccfg, false),\n+ MULTI_EXT_CFG_BOOL(\"sdtrig\", ext_sdtrig, true),\n MULTI_EXT_CFG_BOOL(\"smctr\", ext_smctr, false),\n MULTI_EXT_CFG_BOOL(\"ssctr\", ext_ssctr, false),\n MULTI_EXT_CFG_BOOL(\"zifencei\", ext_zifencei, true),\n@@ -2654,8 +2663,42 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {\n NULL\n };\n \n+/*\n+ * DEPRECATED_11.0: just a proxy for ext_sdtrig.\n+ */\n+static void prop_debug_get(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ bool value = RISCV_CPU(obj)->cfg.ext_sdtrig;\n+\n+ visit_type_bool(v, name, &value, errp);\n+}\n+\n+/*\n+ * DEPRECATED_11.0: just a proxy for ext_sdtrig.\n+ */\n+static void prop_debug_set(Object *obj, Visitor *v, const char *name,\n+ void *opaque, Error **errp)\n+{\n+ RISCVCPU *cpu = RISCV_CPU(obj);\n+ bool value;\n+\n+ visit_type_bool(v, name, &value, errp);\n+ cpu->cfg.ext_sdtrig = value;\n+}\n+\n+/*\n+ * DEPRECATED_11.0: just a proxy for ext_sdtrig.\n+ */\n+static const PropertyInfo prop_debug = {\n+ .type = \"bool\",\n+ .description = \"DEPRECATED: use 'sdtrig' instead.\",\n+ .get = prop_debug_get,\n+ .set = prop_debug_set,\n+};\n+\n static const Property riscv_cpu_properties[] = {\n- DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n+ {.name = \"debug\", .info = &prop_debug},\n \n {.name = \"pmu-mask\", .info = &prop_pmu_mask},\n {.name = \"pmu-num\", .info = &prop_pmu_num}, /* Deprecated */\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex 734fa079f2..44235bfaa1 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -46,6 +46,7 @@ BOOL_FIELD(ext_zilsd)\n BOOL_FIELD(ext_zimop)\n BOOL_FIELD(ext_zcmop)\n BOOL_FIELD(ext_ztso)\n+BOOL_FIELD(ext_sdtrig)\n BOOL_FIELD(ext_smstateen)\n BOOL_FIELD(ext_sstc)\n BOOL_FIELD(ext_smcdeleg)\n@@ -159,7 +160,6 @@ BOOL_FIELD(ext_xlrbr)\n \n BOOL_FIELD(mmu)\n BOOL_FIELD(pmp)\n-BOOL_FIELD(debug)\n BOOL_FIELD(misa_w)\n \n BOOL_FIELD(short_isa_string)\ndiff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex cfd076b368..93b4864933 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -776,7 +776,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno)\n \n static RISCVException debug(CPURISCVState *env, int csrno)\n {\n- if (riscv_cpu_cfg(env)->debug) {\n+ if (riscv_cpu_cfg(env)->ext_sdtrig) {\n return RISCV_EXCP_NONE;\n }\n \ndiff --git a/target/riscv/machine.c b/target/riscv/machine.c\nindex 09c032a879..62c51c8033 100644\n--- a/target/riscv/machine.c\n+++ b/target/riscv/machine.c\n@@ -218,14 +218,14 @@ static const VMStateDescription vmstate_kvmtimer = {\n };\n #endif\n \n-static bool debug_needed(void *opaque)\n+static bool sdtrig_needed(void *opaque)\n {\n RISCVCPU *cpu = opaque;\n \n- return cpu->cfg.debug;\n+ return cpu->cfg.ext_sdtrig;\n }\n \n-static int debug_post_load(void *opaque, int version_id)\n+static int sdtrig_post_load(void *opaque, int version_id)\n {\n RISCVCPU *cpu = opaque;\n CPURISCVState *env = &cpu->env;\n@@ -237,12 +237,12 @@ static int debug_post_load(void *opaque, int version_id)\n return 0;\n }\n \n-static const VMStateDescription vmstate_debug = {\n- .name = \"cpu/debug\",\n- .version_id = 2,\n- .minimum_version_id = 2,\n- .needed = debug_needed,\n- .post_load = debug_post_load,\n+static const VMStateDescription vmstate_sdtrig = {\n+ .name = \"cpu/sdtrig\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = sdtrig_needed,\n+ .post_load = sdtrig_post_load,\n .fields = (const VMStateField[]) {\n VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),\n VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),\n@@ -425,8 +425,8 @@ static const VMStateDescription vmstate_sstc = {\n \n const VMStateDescription vmstate_riscv_cpu = {\n .name = \"cpu\",\n- .version_id = 11,\n- .minimum_version_id = 11,\n+ .version_id = 12,\n+ .minimum_version_id = 12,\n .post_load = riscv_cpu_post_load,\n .fields = (const VMStateField[]) {\n VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),\n@@ -492,13 +492,13 @@ const VMStateDescription vmstate_riscv_cpu = {\n &vmstate_kvmtimer,\n #endif\n &vmstate_envcfg,\n- &vmstate_debug,\n &vmstate_smstateen,\n &vmstate_jvt,\n &vmstate_elp,\n &vmstate_ssp,\n &vmstate_ctr,\n &vmstate_sstc,\n+ &vmstate_sdtrig,\n NULL\n }\n };\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f7808895..0613450691 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -180,7 +180,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED;\n }\n \n- if (cpu->cfg.debug && !icount_enabled()) {\n+ if (cpu->cfg.ext_sdtrig && !icount_enabled()) {\n flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);\n }\n #endif\n", "prefixes": [ "v6", "1/7" ] }