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GET /api/1.1/patches/2222285/?format=api
{ "id": 2222285, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222285/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260411070637.72421-1-james.hilliard1@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260411070637.72421-1-james.hilliard1@gmail.com>", "date": "2026-04-11T07:06:27", "name": "[1/9] linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cee658020a507d82a4b3b8a9c1c1962f4173029c", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.1/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260411070637.72421-1-james.hilliard1@gmail.com/mbox/", "series": [ { "id": 499531, "url": "http://patchwork.ozlabs.org/api/1.1/series/499531/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499531", "date": "2026-04-11T07:06:33", "name": "[1/9] linux-user/mips, target/mips: honor MIPS_FIXADE for unaligned accesses", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499531/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222285/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222285/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=q28/4fpo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oi1-x235.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Linux/MIPS enables software fixups for user-mode unaligned scalar\naccesses by default through MIPS_FIXADE/TIF_FIXADE. QEMU linux-user did\nnot model that ABI, so MIPS guests took fatal AdEL/AdES exceptions\nunless translation was forced to use unaligned host accesses.\n\nReplace the target-specific workaround with a generic MIPS linux-user\nimplementation:\n\n- key MIPS translation blocks on the linux-user unaligned policy,\n- implement sysmips(MIPS_FIXADE) to toggle that policy, and\n- raise SIGBUS/BUS_ADRALN when fixups are disabled.\n\nThis makes the default behaviour match native Linux/MIPS more closely\nand keeps the signal semantics consistent with the kernel ABI.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\n linux-user/mips/cpu_loop.c | 5 +++++\n linux-user/mips/target_syscall.h | 4 ++++\n linux-user/mips64/target_syscall.h | 4 ++++\n linux-user/syscall.c | 24 ++++++++++++++++++++++++\n target/mips/cpu.c | 8 ++++++--\n target/mips/cpu.h | 4 ++++\n target/mips/tcg/translate.c | 6 +++++-\n 7 files changed, 52 insertions(+), 3 deletions(-)", "diff": "diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c\nindex fa264b27ec..ff9d293c29 100644\n--- a/linux-user/mips/cpu_loop.c\n+++ b/linux-user/mips/cpu_loop.c\n@@ -161,6 +161,11 @@ done_syscall:\n case EXCP_DSPDIS:\n force_sig(TARGET_SIGILL);\n break;\n+ case EXCP_AdEL:\n+ case EXCP_AdES:\n+ force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,\n+ env->CP0_BadVAddr);\n+ break;\n case EXCP_INTERRUPT:\n /* just indicate that signals should be handled asap */\n break;\ndiff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h\nindex dfcdf320b7..f8dc5c4e06 100644\n--- a/linux-user/mips/target_syscall.h\n+++ b/linux-user/mips/target_syscall.h\n@@ -10,6 +10,10 @@\n #define TARGET_MCL_ONFAULT 4\n \n #define TARGET_FORCE_SHMLBA\n+#define TARGET_SYSMIPS_SETNAME 1\n+#define TARGET_SYSMIPS_FLUSH_CACHE 3\n+#define TARGET_SYSMIPS_FIXADE 7\n+#define TARGET_SYSMIPS_ATOMIC_SET 2001\n \n static inline abi_ulong target_shmlba(CPUMIPSState *env)\n {\ndiff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h\nindex 9135bf5e8b..d786fba5a9 100644\n--- a/linux-user/mips64/target_syscall.h\n+++ b/linux-user/mips64/target_syscall.h\n@@ -10,6 +10,10 @@\n #define TARGET_MCL_ONFAULT 4\n \n #define TARGET_FORCE_SHMLBA\n+#define TARGET_SYSMIPS_SETNAME 1\n+#define TARGET_SYSMIPS_FLUSH_CACHE 3\n+#define TARGET_SYSMIPS_FIXADE 7\n+#define TARGET_SYSMIPS_ATOMIC_SET 2001\n \n static inline abi_ulong target_shmlba(CPUMIPSState *env)\n {\ndiff --git a/linux-user/syscall.c b/linux-user/syscall.c\nindex f4b74ad350..4f58eb4afe 100644\n--- a/linux-user/syscall.c\n+++ b/linux-user/syscall.c\n@@ -6595,6 +6595,26 @@ static abi_long do_prctl_syscall_user_dispatch(CPUArchState *env,\n }\n }\n \n+#ifdef TARGET_NR_sysmips\n+static abi_long do_sysmips(CPUArchState *env, abi_long cmd, abi_long arg1)\n+{\n+ CPUState *cs = env_cpu(env);\n+\n+ switch (cmd) {\n+ case TARGET_SYSMIPS_FIXADE:\n+ if (arg1 & ~3) {\n+ return -TARGET_EINVAL;\n+ }\n+ cs->prctl_unalign_sigbus = !(arg1 & 1);\n+ return 0;\n+ case TARGET_SYSMIPS_FLUSH_CACHE:\n+ return 0;\n+ default:\n+ return -TARGET_EINVAL;\n+ }\n+}\n+#endif\n+\n static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,\n abi_long arg3, abi_long arg4, abi_long arg5)\n {\n@@ -12067,6 +12087,10 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,\n case TARGET_NR_prctl:\n return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5);\n break;\n+#ifdef TARGET_NR_sysmips\n+ case TARGET_NR_sysmips:\n+ return do_sysmips(cpu_env, arg1, arg2);\n+#endif\n #ifdef TARGET_NR_arch_prctl\n case TARGET_NR_arch_prctl:\n return do_arch_prctl(cpu_env, arg1, arg2);\ndiff --git a/target/mips/cpu.c b/target/mips/cpu.c\nindex 5f88c077db..ec70c10985 100644\n--- a/target/mips/cpu.c\n+++ b/target/mips/cpu.c\n@@ -555,11 +555,15 @@ static int mips_cpu_mmu_index(CPUState *cs, bool ifunc)\n static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs)\n {\n CPUMIPSState *env = cpu_env(cs);\n+ uint32_t flags = env->hflags & MIPS_HFLAG_TB_MASK;\n+\n+#ifdef CONFIG_USER_ONLY\n+ flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus;\n+#endif\n \n return (TCGTBCPUState){\n .pc = env->active_tc.PC,\n- .flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |\n- MIPS_HFLAG_HWRENA_ULR),\n+ .flags = flags,\n };\n }\n \ndiff --git a/target/mips/cpu.h b/target/mips/cpu.h\nindex ed662135cb..ac81470576 100644\n--- a/target/mips/cpu.h\n+++ b/target/mips/cpu.h\n@@ -1161,6 +1161,10 @@ typedef struct CPUArchState {\n #define MIPS_HFLAG_ELPA 0x4000000\n #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */\n #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */\n+#define MIPS_HFLAG_TB_MASK (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | \\\n+ MIPS_HFLAG_HWRENA_ULR)\n+\n+#define TB_FLAG_UNALIGN 0x40000000\n target_ulong btarget; /* Jump / branch target */\n target_ulong bcond; /* Branch condition (if needed) */\n \ndiff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c\nindex 54849e9ff1..2e3fe1fa16 100644\n--- a/target/mips/tcg/translate.c\n+++ b/target/mips/tcg/translate.c\n@@ -15067,6 +15067,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n {\n DisasContext *ctx = container_of(dcbase, DisasContext, base);\n CPUMIPSState *env = cpu_env(cs);\n+ uint32_t tb_flags = ctx->base.tb->flags;\n \n ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;\n ctx->saved_pc = -1;\n@@ -15089,7 +15090,7 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift;\n ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1;\n /* Restore delay slot state from the tb context. */\n- ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */\n+ ctx->hflags = tb_flags & MIPS_HFLAG_TB_MASK;\n ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1;\n ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) ||\n (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F));\n@@ -15109,6 +15110,9 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)\n ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&\n (ctx->insn_flags & (ISA_MIPS_R6 |\n INSN_LOONGSON3A))) ? MO_UNALN : MO_ALIGN;\n+ if (tb_flags & TB_FLAG_UNALIGN) {\n+ ctx->default_tcg_memop_mask = MO_UNALN;\n+ }\n \n /*\n * Execute a branch and its delay slot as a single instruction.\n", "prefixes": [ "1/9" ] }