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GET /api/1.1/patches/2222204/?format=api
{ "id": 2222204, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222204/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260410200628.19378-3-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260410200628.19378-3-philmd@linaro.org>", "date": "2026-04-10T20:06:21", "name": "[2/9] target/arm: Explode MO_TExx -> MO_TE | MO_xx", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2acbde88758c395a7b6e9ebe1057e19444183738", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.1/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260410200628.19378-3-philmd@linaro.org/mbox/", "series": [ { "id": 499501, "url": "http://patchwork.ozlabs.org/api/1.1/series/499501/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499501", "date": "2026-04-10T20:06:19", "name": "target/arm: Remove MO_TE to compile MVE/M helpers once", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499501/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222204/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222204/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bS/aignY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::335;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Extract the implicit MO_TE definition in order to replace\nit in the next commit.\n\nMechanical change using:\n\n $ for n in UW UL UQ UO SW SL SQ; do \\\n sed -i -e \"s/MO_TE$n/MO_TE | MO_$n/\" \\\n $(git grep -l MO_TE$n target/arm); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/arm/tcg/m_helper.c | 6 +--\n target/arm/tcg/mve_helper.c | 79 ++++++++++++++++++++-----------------\n 2 files changed, 45 insertions(+), 40 deletions(-)", "diff": "diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c\nindex a0cb8cb021e..f5954ce9bf9 100644\n--- a/target/arm/tcg/m_helper.c\n+++ b/target/arm/tcg/m_helper.c\n@@ -634,7 +634,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n \n /* Note that these stores can throw exceptions on MPU faults */\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN,\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN,\n arm_to_core_mmu_idx(mmu_idx));\n cpu_stl_mmu(env, sp, nextinst, oi, GETPC());\n cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC());\n@@ -1055,7 +1055,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)\n bool lspact = env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK;\n uintptr_t ra = GETPC();\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN,\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN,\n arm_to_core_mmu_idx(mmu_idx));\n \n assert(env->v7m.secure);\n@@ -1131,7 +1131,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)\n ARMCPU *cpu = env_archcpu(env);\n uintptr_t ra = GETPC();\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN,\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN,\n arm_to_core_mmu_idx(mmu_idx));\n \n /* fptr is the value of Rn, the frame pointer we load the FP regs from */\ndiff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c\nindex a67d90d6c75..cc58e0502f5 100644\n--- a/target/arm/tcg/mve_helper.c\n+++ b/target/arm/tcg/mve_helper.c\n@@ -194,23 +194,23 @@ static void mve_advance_vpt(CPUARMState *env)\n }\n \n DO_VLDR(vldrb, MO_UB, 1, uint8_t, ldb, 1, uint8_t)\n-DO_VLDR(vldrh, MO_TEUW, 2, uint16_t, ldw, 2, uint16_t)\n-DO_VLDR(vldrw, MO_TEUL, 4, uint32_t, ldl, 4, uint32_t)\n+DO_VLDR(vldrh, MO_TE | MO_UW, 2, uint16_t, ldw, 2, uint16_t)\n+DO_VLDR(vldrw, MO_TE | MO_UL, 4, uint32_t, ldl, 4, uint32_t)\n \n DO_VSTR(vstrb, MO_UB, 1, stb, 1, uint8_t)\n-DO_VSTR(vstrh, MO_TEUW, 2, stw, 2, uint16_t)\n-DO_VSTR(vstrw, MO_TEUL, 4, stl, 4, uint32_t)\n+DO_VSTR(vstrh, MO_TE | MO_UW, 2, stw, 2, uint16_t)\n+DO_VSTR(vstrw, MO_TE | MO_UL, 4, stl, 4, uint32_t)\n \n DO_VLDR(vldrb_sh, MO_SB, 1, int8_t, ldb, 2, int16_t)\n DO_VLDR(vldrb_sw, MO_SB, 1, int8_t, ldb, 4, int32_t)\n DO_VLDR(vldrb_uh, MO_UB, 1, uint8_t, ldb, 2, uint16_t)\n DO_VLDR(vldrb_uw, MO_UB, 1, uint8_t, ldb, 4, uint32_t)\n-DO_VLDR(vldrh_sw, MO_TESW, 2, int16_t, ldw, 4, int32_t)\n-DO_VLDR(vldrh_uw, MO_TEUW, 2, uint16_t, ldw, 4, uint32_t)\n+DO_VLDR(vldrh_sw, MO_TE | MO_SW, 2, int16_t, ldw, 4, int32_t)\n+DO_VLDR(vldrh_uw, MO_TE | MO_UW, 2, uint16_t, ldw, 4, uint32_t)\n \n DO_VSTR(vstrb_h, MO_UB, 1, stb, 2, int16_t)\n DO_VSTR(vstrb_w, MO_UB, 1, stb, 4, int32_t)\n-DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t)\n+DO_VSTR(vstrh_w, MO_TE | MO_UW, 2, stw, 4, int32_t)\n \n #undef DO_VLDR\n #undef DO_VSTR\n@@ -295,7 +295,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \\\n if (!(eci_mask & 1)) { \\\n continue; \\\n@@ -321,7 +321,7 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t)\n unsigned e; \\\n uint32_t addr; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (e = 0; e < 16 / 4; e++, mask >>= 4, eci_mask >>= 4) { \\\n if (!(eci_mask & 1)) { \\\n continue; \\\n@@ -345,42 +345,47 @@ DO_VSTR(vstrh_w, MO_TEUW, 2, stw, 4, int32_t)\n \n DO_VLDR_SG(vldrb_sg_sh, MO_SB, int8_t, ldb, 2, int16_t, uint16_t, ADDR_ADD, false)\n DO_VLDR_SG(vldrb_sg_sw, MO_SB, int8_t, ldb, 4, int32_t, uint32_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrh_sg_sw, MO_TESW, int16_t, ldw, 4, int32_t, uint32_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrh_sg_sw, MO_TE | MO_SW, int16_t, ldw, 4,\n+ int32_t, uint32_t, ADDR_ADD, false)\n \n DO_VLDR_SG(vldrb_sg_ub, MO_UB, uint8_t, ldb, 1, uint8_t, uint8_t, ADDR_ADD, false)\n DO_VLDR_SG(vldrb_sg_uh, MO_UB, uint8_t, ldb, 2, uint16_t, uint16_t, ADDR_ADD, false)\n DO_VLDR_SG(vldrb_sg_uw, MO_UB, uint8_t, ldb, 4, uint32_t, uint32_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrh_sg_uh, MO_TEUW, uint16_t, ldw, 2, uint16_t, uint16_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrh_sg_uw, MO_TEUW, uint16_t, ldw, 4, uint32_t, uint32_t, ADDR_ADD, false)\n-DO_VLDR_SG(vldrw_sg_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrh_sg_uh, MO_TE | MO_UW, uint16_t, ldw, 2,\n+ uint16_t, uint16_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrh_sg_uw, MO_TE | MO_UW, uint16_t, ldw, 4,\n+ uint32_t, uint32_t, ADDR_ADD, false)\n+DO_VLDR_SG(vldrw_sg_uw, MO_TE | MO_UL, uint32_t, ldl, 4,\n+ uint32_t, uint32_t, ADDR_ADD, false)\n DO_VLDR64_SG(vldrd_sg_ud, ADDR_ADD, false)\n \n-DO_VLDR_SG(vldrh_sg_os_sw, MO_TESW, int16_t, ldw, 4,\n+DO_VLDR_SG(vldrh_sg_os_sw, MO_TE | MO_SW, int16_t, ldw, 4,\n int32_t, uint32_t, ADDR_ADD_OSH, false)\n-DO_VLDR_SG(vldrh_sg_os_uh, MO_TEUW, uint16_t, ldw, 2,\n+DO_VLDR_SG(vldrh_sg_os_uh, MO_TE | MO_UW, uint16_t, ldw, 2,\n uint16_t, uint16_t, ADDR_ADD_OSH, false)\n-DO_VLDR_SG(vldrh_sg_os_uw, MO_TEUW, uint16_t, ldw, 4,\n+DO_VLDR_SG(vldrh_sg_os_uw, MO_TE | MO_UW, uint16_t, ldw, 4,\n uint32_t, uint32_t, ADDR_ADD_OSH, false)\n-DO_VLDR_SG(vldrw_sg_os_uw, MO_TEUL, uint32_t, ldl, 4,\n+DO_VLDR_SG(vldrw_sg_os_uw, MO_TE | MO_UL, uint32_t, ldl, 4,\n uint32_t, uint32_t, ADDR_ADD_OSW, false)\n DO_VLDR64_SG(vldrd_sg_os_ud, ADDR_ADD_OSD, false)\n \n DO_VSTR_SG(vstrb_sg_ub, MO_UB, stb, 1, uint8_t, ADDR_ADD, false)\n DO_VSTR_SG(vstrb_sg_uh, MO_UB, stb, 2, uint16_t, ADDR_ADD, false)\n DO_VSTR_SG(vstrb_sg_uw, MO_UB, stb, 4, uint32_t, ADDR_ADD, false)\n-DO_VSTR_SG(vstrh_sg_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD, false)\n-DO_VSTR_SG(vstrh_sg_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD, false)\n-DO_VSTR_SG(vstrw_sg_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, false)\n+DO_VSTR_SG(vstrh_sg_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD, false)\n+DO_VSTR_SG(vstrh_sg_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD, false)\n+DO_VSTR_SG(vstrw_sg_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, false)\n DO_VSTR64_SG(vstrd_sg_ud, ADDR_ADD, false)\n \n-DO_VSTR_SG(vstrh_sg_os_uh, MO_TEUW, stw, 2, uint16_t, ADDR_ADD_OSH, false)\n-DO_VSTR_SG(vstrh_sg_os_uw, MO_TEUW, stw, 4, uint32_t, ADDR_ADD_OSH, false)\n-DO_VSTR_SG(vstrw_sg_os_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD_OSW, false)\n+DO_VSTR_SG(vstrh_sg_os_uh, MO_TE | MO_UW, stw, 2, uint16_t, ADDR_ADD_OSH, false)\n+DO_VSTR_SG(vstrh_sg_os_uw, MO_TE | MO_UW, stw, 4, uint32_t, ADDR_ADD_OSH, false)\n+DO_VSTR_SG(vstrw_sg_os_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD_OSW, false)\n DO_VSTR64_SG(vstrd_sg_os_ud, ADDR_ADD_OSD, false)\n \n-DO_VLDR_SG(vldrw_sg_wb_uw, MO_TEUL, uint32_t, ldl, 4, uint32_t, uint32_t, ADDR_ADD, true)\n+DO_VLDR_SG(vldrw_sg_wb_uw, MO_TE | MO_UL, uint32_t, ldl, 4,\n+ uint32_t, uint32_t, ADDR_ADD, true)\n DO_VLDR64_SG(vldrd_sg_wb_ud, ADDR_ADD, true)\n-DO_VSTR_SG(vstrw_sg_wb_uw, MO_TEUL, stl, 4, uint32_t, ADDR_ADD, true)\n+DO_VSTR_SG(vstrw_sg_wb_uw, MO_TE | MO_UL, stl, 4, uint32_t, ADDR_ADD, true)\n DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n \n /*\n@@ -408,7 +413,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n static const uint8_t off[4] = { O1, O2, O3, O4 }; \\\n uint32_t addr, data; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -434,7 +439,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n int y; /* y counts 0 2 0 2 */ \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -461,7 +466,7 @@ DO_VSTR64_SG(vstrd_sg_wb_ud, ADDR_ADD, true)\n uint32_t *qd; \\\n int y; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -500,7 +505,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint8_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -526,7 +531,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9)\n int e; \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -551,7 +556,7 @@ DO_VLD4W(vld43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint32_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -582,7 +587,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20)\n static const uint8_t off[4] = { O1, O2, O3, O4 }; \\\n uint32_t addr, data; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -609,7 +614,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20)\n int y; /* y counts 0 2 0 2 */ \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0, y = 0; beat < 4; beat++, mask >>= 4, y ^= 2) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -635,7 +640,7 @@ DO_VLD2W(vld21w, 8, 12, 16, 20)\n uint32_t *qd; \\\n int y; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -674,7 +679,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint8_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -701,7 +706,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9)\n int e; \\\n uint16_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n@@ -727,7 +732,7 @@ DO_VST4W(vst43w, 6, 7, 8, 9)\n uint32_t addr, data; \\\n uint32_t *qd; \\\n int mmu_idx = arm_to_core_mmu_idx(arm_mmu_idx(env)); \\\n- MemOpIdx oi = make_memop_idx(MO_TEUL | MO_ALIGN, mmu_idx); \\\n+ MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN, mmu_idx);\\\n for (beat = 0; beat < 4; beat++, mask >>= 4) { \\\n if ((mask & 1) == 0) { \\\n /* ECI says skip this beat */ \\\n", "prefixes": [ "2/9" ] }