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GET /api/1.1/patches/2222202/?format=api
{ "id": 2222202, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222202/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260410200628.19378-9-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260410200628.19378-9-philmd@linaro.org>", "date": "2026-04-10T20:06:27", "name": "[8/9] target/arm: Replace MO_TE -> mo_endian() for Cortex-M helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "75cabacd382e54601a133f425a50374e2809ed90", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.1/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260410200628.19378-9-philmd@linaro.org/mbox/", "series": [ { "id": 499501, "url": "http://patchwork.ozlabs.org/api/1.1/series/499501/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499501", "date": "2026-04-10T20:06:19", "name": "target/arm: Remove MO_TE to compile MVE/M helpers once", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499501/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222202/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222202/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gDIiVJod;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::330;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/arm/tcg/m_helper.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c\nindex f5954ce9bf9..1bec8e9aea3 100644\n--- a/target/arm/tcg/m_helper.c\n+++ b/target/arm/tcg/m_helper.c\n@@ -634,7 +634,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)\n \n /* Note that these stores can throw exceptions on MPU faults */\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN,\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN,\n arm_to_core_mmu_idx(mmu_idx));\n cpu_stl_mmu(env, sp, nextinst, oi, GETPC());\n cpu_stl_mmu(env, sp + 4, saved_psr, oi, GETPC());\n@@ -1055,7 +1055,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr)\n bool lspact = env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK;\n uintptr_t ra = GETPC();\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN,\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN,\n arm_to_core_mmu_idx(mmu_idx));\n \n assert(env->v7m.secure);\n@@ -1131,7 +1131,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr)\n ARMCPU *cpu = env_archcpu(env);\n uintptr_t ra = GETPC();\n ARMMMUIdx mmu_idx = arm_mmu_idx(env);\n- MemOpIdx oi = make_memop_idx(MO_TE | MO_UL | MO_ALIGN,\n+ MemOpIdx oi = make_memop_idx(mo_endian(env) | MO_UL | MO_ALIGN,\n arm_to_core_mmu_idx(mmu_idx));\n \n /* fptr is the value of Rn, the frame pointer we load the FP regs from */\n", "prefixes": [ "8/9" ] }