Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2222061/?format=api
{ "id": 2222061, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222061/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/c20a21aad60f09fe7e971d81503370a782c9319f.1775843299.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<c20a21aad60f09fe7e971d81503370a782c9319f.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "date": "2026-04-10T17:56:02", "name": "[v4,14/16] tests/hexagon: add tests for v68 HVX IEEE float conversions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "74fee437f9b6645d90fbf101688b279a7e0e4517", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/1.1/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/c20a21aad60f09fe7e971d81503370a782c9319f.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 499491, "url": "http://patchwork.ozlabs.org/api/1.1/series/499491/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491", "date": "2026-04-10T17:55:50", "name": "hexagon: add missing HVX float instructions", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499491/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222061/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222061/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=d6azzeHu;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=J1lGF1zM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsl2D1w1Jz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 11 Apr 2026 04:00:04 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wBG5u-0006so-3A; Fri, 10 Apr 2026 13:56:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <matheus.bernardino@oss.qualcomm.com>)\n id 1wBG5r-0006rm-RW\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:35 -0400", "from mx0a-0031df01.pphosted.com ([205.220.168.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <matheus.bernardino@oss.qualcomm.com>)\n id 1wBG5l-0001gA-TJ\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:33 -0400", "from pps.filterd (m0279865.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63AHP9so707656\n for <qemu-devel@nongnu.org>; Fri, 10 Apr 2026 17:56:24 GMT", "from mail-dy1-f199.google.com (mail-dy1-f199.google.com\n [74.125.82.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deudj2dhq-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <qemu-devel@nongnu.org>; Fri, 10 Apr 2026 17:56:24 +0000 (GMT)", "by mail-dy1-f199.google.com with SMTP id\n 5a478bee46e88-2d443c3b094so4176171eec.1\n for <qemu-devel@nongnu.org>; Fri, 10 Apr 2026 10:56:24 -0700 (PDT)", "from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n a92af1059eb24-12c3459f7ffsm4256271c88.3.2026.04.10.10.56.20\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 10 Apr 2026 10:56:21 -0700 (PDT)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=V6nVKixGSjR\n GXMplnHG6wHz1J9IW5gbrlupSNq0KwoE=; b=d6azzeHuQIsWtlC0SCSG/Xrl4MN\n DSdV5PVdO+m06k+bPWmbts76mJ8hlYzRqzqZoy+23vdMiIlhN/5P+P0CE3RbKIdF\n nb1PfS6f8NTSQQXYtfYYF/o14i0I6K2IXMzOEhFPYElJ4KcrYUG2i+MIrNpz6HM4\n ufsdJ2fTpb0qpVRqdsNFwHomqRExImjkWrDWqEA8gyRINXMwOYM9+K90bHYsCMjk\n RjexjvKoSKrKauDEw2LLknMe5WfhxAA3dAGKKwOKk+dTXB5pt1+0JSIuPwt0xWs3\n Lz+59W0x/WBXoYpOF/ONh7rV65ADwRbMEctI5O0XVUHP47NfdGhMTXXYHyA==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775843783; x=1776448583; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=V6nVKixGSjRGXMplnHG6wHz1J9IW5gbrlupSNq0KwoE=;\n b=J1lGF1zMxKiExdOw4dVokylJ/RBfXxKfV4oRBk7z8TkZSQZOcDr4T11oW3yjmEL8wY\n VV6REQ0odjaGQ6Rjl/nV7zLS98So1GPd1fjEnoisI5JGv3Or/f8xUZJWSwez6xBAlrMS\n gv2ZzhOIWPlmh7TdgPxZjkcRS5OUPnkntHvVBudQG4ETdpdjx/r8xh4WSZ3Ap/AXroZz\n zfMw+CA16GpuAEpjXsvCdWS3RUqeM0gpzyqnX/ysp/H/0gQx1IsglAbhjfpgi9ShGtiU\n HLSsTd0tjzGbt+hEM/AIONKvVjDUCrngI1+Q+jrlKYRTBU4w4LgbKm8UvmflJtkZ9URM\n lcEA==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775843783; x=1776448583;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=V6nVKixGSjRGXMplnHG6wHz1J9IW5gbrlupSNq0KwoE=;\n b=oPC9ucwcsm4C1XmaLGT4UnvYgnjA2awnSMHv6v9DDVmqEcNdJo6EepnvbvReLAdJPA\n flxJE80LX6zFfCIUr1ognByYh8I7O9poxwgqXZaOhj4X621FSeVjdff4tOu04gbfZLob\n DoRjI8UntaBs0wYtSmABO/MDliL77mkNhR9V05CBWtm4N5rOk5MwswCo8UCkEVmu/Cnv\n 1XHMweMDG9K0kTbzd0QrM6osOkxCNuQUpjR8MOrvhjnLeI0CNVV+vOfH/AaTolHbqOF+\n 1btr0KwbIOdzDpPQr/CdToDbaR1bKIIFb14zLke8h68qHCAsYwkxrq7NJFLiDi5ecJDz\n ki2w==", "X-Gm-Message-State": "AOJu0YxTWR9j2oZ+iAafWLC+yqoGS7FbWpAp8pJH6+T4Qj+/D9CABjSR\n 8I7+2KASwYDYJ3G+MIZh4m2grWIhspJ0SYsF4hpUsk4bEibQXZkrDj6fqeeAUYNHXwP+w5rfI4T\n V5WHBM7qNUO/qTAcG2zb5c6Xv32zHz1vhPKeW70HzYSUShqbxWg34fhaRvaYvlsy3PEgY", "X-Gm-Gg": "AeBDieuBWBVbFk96VD9NBlr8s7RYoVyu4R40ogPQ4lI0v2a1GjBYP6FI8kgVNd03o58\n Dl0aK8Ud0n9iSGkUH+DP6Zv6nHQBFyklz76avNwPtnV79Ko48SlJAjjlSvC9eOEAWPD1vKv89KX\n XgZn7cuHKZf0WC130dT5y3+vVWRwr27HryPFG2coU1tp8/kzKvLJi81YqFygL66lUfYE1pL0MPZ\n Tj3tBvW/YI1sVRObxB36c+pZAmF0tg2YcU+zTaIli0q8J2nO5oRFx6DSS8LTTUvkokke/qWea5T\n G9xX10jW9hAoyPXCWP5gp0cTTzehRoCAtcNdW7MS/lRvAlP6I2r8uyrarugPeUXJhxvnSde7gCh\n 7RdnQ3F6xioyfxECyic7mZKDQqx7TGtIk07dUWjr3frEq1swISfhv2AGGNf/MraM2IGE3fgKehj\n j/DUp4uQYf", "X-Received": [ "by 2002:a05:7022:f92:b0:128:bae0:e043 with SMTP id\n a92af1059eb24-12c34f14057mr2569948c88.31.1775843782433;\n Fri, 10 Apr 2026 10:56:22 -0700 (PDT)", "by 2002:a05:7022:f92:b0:128:bae0:e043 with SMTP id\n a92af1059eb24-12c34f14057mr2569907c88.31.1775843781697;\n Fri, 10 Apr 2026 10:56:21 -0700 (PDT)" ], "From": "Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v4 14/16] tests/hexagon: add tests for v68 HVX IEEE float\n conversions", "Date": "Fri, 10 Apr 2026 10:56:02 -0700", "Message-Id": "\n <c20a21aad60f09fe7e971d81503370a782c9319f.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "LQxqnRYlL8hfFVOOhp_Aub7f0ltPhE8M", "X-Proofpoint-GUID": "LQxqnRYlL8hfFVOOhp_Aub7f0ltPhE8M", "X-Authority-Analysis": "v=2.4 cv=cKfQdFeN c=1 sm=1 tr=0 ts=69d939c8 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=pGLkceISAAAA:8\n a=EUspDBNiAAAA:8 a=OZRFAO6Uk6ULta4fWVgA:9 a=scEy_gLbYbu1JhEsrz4S:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDEwMDE2OCBTYWx0ZWRfX49/UIBY06b8K\n PEcmplWEwbb70qpjO7I/0yS19lqPZEni+It3GSstP47xajLx5Mv1Hbk/w6Wm39hzct6CwnLMT2P\n HrjVRtPinqvnnsaZeo2mJg2Tv3+fbS0/44Xk03ONqvT2rVpTu28vxB7U0bBkRV4eeekVtwGbNad\n 5wlLbegySHlL+JVzbfnfA7IzKSIryNhqo0fLLNIsb+Av15S0ydMbl46mwpxJfxLJ6crBjcBlEAM\n syOnPEXI/gRRXX2hitMpesWqd0nUL/oKISWMOTtJGkpSnNm8u1TScZmLzRKgIJU6jvGlRUPTa6Q\n wlteHy5Ntz9DIDGVFUFJpVbsSOdayHE3EMOMa8AOXj274BJpwfnFj2CQCOSHnvVOUflyhXAi2Tw\n FDnTxYlVla0NsAweHxZUcW4NpJ29giRL1xkcW6C5LRy2oSabnTlFz5P8R17TYRr438pcqbXAlFN\n eX5z8L5wCyEnPKjTQyw==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0\n adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100168", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n tests/tcg/hexagon/hex_test.h | 14 +++\n tests/tcg/hexagon/hvx_misc.h | 2 +\n tests/tcg/hexagon/fp_hvx_cvt.c | 188 ++++++++++++++++++++++++++++++\n tests/tcg/hexagon/Makefile.target | 3 +\n 4 files changed, 207 insertions(+)\n create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c", "diff": "diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h\nindex e7a6644d41..d5da8ad240 100644\n--- a/tests/tcg/hexagon/hex_test.h\n+++ b/tests/tcg/hexagon/hex_test.h\n@@ -111,6 +111,20 @@ static inline void __check64_ne(int line, uint64_t val, uint64_t expect)\n \"usr = r2\\n\\t\"\n \n /* Some useful floating point values */\n+const uint16_t HF_INF = 0x7c00;\n+const uint16_t HF_INF_neg = 0xfc00;\n+const uint16_t HF_QNaN = 0x7e00;\n+const uint16_t HF_SNaN = 0x7d00;\n+const uint16_t HF_QNaN_neg = 0xfe00;\n+const uint16_t HF_zero = 0x0000;\n+const uint16_t HF_zero_neg = 0x8000;\n+const uint16_t HF_one = 0x3c00;\n+const uint16_t HF_one_recip = 0x3bf9;\n+const uint16_t HF_two = 0x4000;\n+const uint16_t HF_small_neg = 0x8010;\n+const uint16_t HF_any = 0x3c00;\n+const uint16_t HF_neg_two = 0xc000;\n+\n const uint32_t SF_INF = 0x7f800000;\n const uint32_t SF_INF_neg = 0xff800000;\n const uint32_t SF_QNaN = 0x7fc00000;\ndiff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h\nindex 0330cb289d..43de20da6a 100644\n--- a/tests/tcg/hexagon/hvx_misc.h\n+++ b/tests/tcg/hexagon/hvx_misc.h\n@@ -69,7 +69,9 @@ CHECK_OUTPUT_FUNC(d, 8)\n CHECK_OUTPUT_FUNC(w, 4)\n CHECK_OUTPUT_FUNC(sf, 4)\n CHECK_OUTPUT_FUNC(h, 2)\n+CHECK_OUTPUT_FUNC(uh, 2)\n CHECK_OUTPUT_FUNC(hf, 2)\n+CHECK_OUTPUT_FUNC(ub, 1)\n CHECK_OUTPUT_FUNC(b, 1)\n \n static inline void init_buffers(void)\ndiff --git a/tests/tcg/hexagon/fp_hvx_cvt.c b/tests/tcg/hexagon/fp_hvx_cvt.c\nnew file mode 100644\nindex 0000000000..71c3f0fd4f\n--- /dev/null\n+++ b/tests/tcg/hexagon/fp_hvx_cvt.c\n@@ -0,0 +1,188 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <string.h>\n+#include <hexagon_types.h>\n+#include <hvx_hexagon_protos.h>\n+\n+#if __HEXAGON_ARCH__ > 75\n+#error \"After v75, compiler will replace some FP HVX instructions.\"\n+#endif\n+\n+int err;\n+#include \"hvx_misc.h\"\n+#include \"hex_test.h\"\n+\n+#define TEST_EXP(TO, FROM, VAL, EXP) do { \\\n+ ((MMVector *)&buffer)->FROM[index] = VAL; \\\n+ expect[0].TO[index] = EXP; \\\n+ index++; \\\n+} while (0)\n+\n+#define DEF_TEST_CVT(TO, FROM, TESTS) \\\n+ static void test_vcvt_##TO##_##FROM(void) \\\n+ { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \\\n+ HVX_Vector buffer; \\\n+ int index = 0; \\\n+ memset(&buffer, 0, sizeof(buffer)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ TESTS \\\n+ *hvx_output = Q6_V##TO##_vcvt_V##FROM(buffer); \\\n+ check_output_##TO(__LINE__, 1); \\\n+ }\n+\n+DEF_TEST_CVT(uh, hf, { \\\n+ TEST_EXP(uh, hf, HF_QNaN, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_SNaN, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_QNaN_neg, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_INF, UINT16_MAX); \\\n+ TEST_EXP(uh, hf, HF_INF_neg, 0); \\\n+ TEST_EXP(uh, hf, HF_neg_two, 0); \\\n+ TEST_EXP(uh, hf, HF_zero_neg, 0); \\\n+ TEST_EXP(uh, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP(uh, hf, HF_one_recip, 1); \\\n+})\n+\n+DEF_TEST_CVT(h, hf, { \\\n+ TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_QNaN_neg, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_INF, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \\\n+ TEST_EXP(h, hf, HF_neg_two, -2); \\\n+ TEST_EXP(h, hf, HF_zero_neg, 0); \\\n+ TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP(h, hf, HF_one_recip, 1); \\\n+})\n+\n+/*\n+ * Some cvt operations take two vectors as input and perform the following:\n+ * VdV.TO[4*i] = OP(VuV.FROM[2*i]);\n+ * VdV.TO[4*i+1] = OP(VuV.FROM[2*i+1]);\n+ * VdV.TO[4*i+2] = OP(VvV.FROM[2*i]);\n+ * VdV.TO[4*i+3] = OP(VvV.FROM[2*i+1]))\n+ * We use bf_index and index in a way that the tests are always done either\n+ * using the first or third line of the above snippet.\n+ */\n+#define TEST_EXP_2(TO, FROM, VAL, EXP) do { \\\n+ ((MMVector *)&buffers[bf_index])->FROM[2 * index] = VAL; \\\n+ expect[0].TO[(4 * index) + (2 * bf_index)] = EXP; \\\n+ index++; \\\n+ bf_index = (bf_index + 1) % 2; \\\n+} while (0)\n+\n+#define DEF_TEST_CVT_2(TO, FROM, TESTS) \\\n+ static void test_vcvt_##TO##_##FROM(void) \\\n+ { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \\\n+ HVX_Vector buffers[2]; \\\n+ int index = 0, bf_index = 0; \\\n+ memset(&buffers, 0, sizeof(buffers)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ TESTS \\\n+ *hvx_output = Q6_V##TO##_vcvt_V##FROM##V##FROM(buffers[0], buffers[1]); \\\n+ check_output_##TO(__LINE__, 1); \\\n+ }\n+\n+DEF_TEST_CVT_2(ub, hf, { \\\n+ TEST_EXP_2(ub, hf, HF_QNaN, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_SNaN, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_QNaN_neg, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_INF, UINT8_MAX); \\\n+ TEST_EXP_2(ub, hf, HF_INF_neg, 0); \\\n+ TEST_EXP_2(ub, hf, HF_small_neg, 0); \\\n+ TEST_EXP_2(ub, hf, HF_neg_two, 0); \\\n+ TEST_EXP_2(ub, hf, HF_zero_neg, 0); \\\n+ TEST_EXP_2(ub, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP_2(ub, hf, HF_one_recip, 1); \\\n+})\n+\n+DEF_TEST_CVT_2(b, hf, { \\\n+ TEST_EXP_2(b, hf, HF_QNaN, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_SNaN, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_QNaN_neg, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_INF, INT8_MAX); \\\n+ TEST_EXP_2(b, hf, HF_INF_neg, INT8_MIN); \\\n+ TEST_EXP_2(b, hf, HF_small_neg, 0); \\\n+ TEST_EXP_2(b, hf, HF_neg_two, -2); \\\n+ TEST_EXP_2(b, hf, HF_zero_neg, 0); \\\n+ TEST_EXP_2(b, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP_2(b, hf, HF_one_recip, 1); \\\n+})\n+\n+#define DEF_TEST_VCONV(TO, FROM, TESTS) \\\n+ static void test_vconv_##TO##_##FROM(void) \\\n+ { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \\\n+ HVX_Vector buffer; \\\n+ int index = 0; \\\n+ memset(&buffer, 0, sizeof(buffer)); \\\n+ memset(expect, 0, sizeof(expect)); \\\n+ TESTS \\\n+ *hvx_output = Q6_V##TO##_equals_V##FROM(buffer); \\\n+ check_output_##TO(__LINE__, 1); \\\n+ }\n+\n+DEF_TEST_VCONV(w, sf, { \\\n+ TEST_EXP(w, sf, SF_QNaN, INT32_MAX); \\\n+ TEST_EXP(w, sf, SF_SNaN, INT32_MAX); \\\n+ TEST_EXP(w, sf, SF_QNaN_neg, INT32_MIN); \\\n+ TEST_EXP(w, sf, SF_INF, INT32_MAX); \\\n+ TEST_EXP(w, sf, SF_INF_neg, INT32_MIN); \\\n+ TEST_EXP(w, sf, SF_small_neg, 0); \\\n+ TEST_EXP(w, sf, SF_neg_two, -2); \\\n+ TEST_EXP(w, sf, SF_zero_neg, 0); \\\n+ TEST_EXP(w, sf, raw_sf(2.1f), 2); \\\n+ TEST_EXP(w, sf, raw_sf(2.8f), 2); \\\n+})\n+\n+DEF_TEST_VCONV(h, hf, { \\\n+ TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_QNaN_neg, INT16_MIN); \\\n+ TEST_EXP(h, hf, HF_INF, INT16_MAX); \\\n+ TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \\\n+ TEST_EXP(h, hf, HF_small_neg, 0); \\\n+ TEST_EXP(h, hf, HF_neg_two, -2); \\\n+ TEST_EXP(h, hf, HF_zero_neg, 0); \\\n+ TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \\\n+ TEST_EXP(h, hf, raw_hf((_Float16)2.8), 2); \\\n+})\n+\n+DEF_TEST_VCONV(hf, h, { \\\n+ TEST_EXP(hf, h, 0, HF_zero); \\\n+ TEST_EXP(hf, h, 2, HF_two); \\\n+ TEST_EXP(hf, h, -2, HF_neg_two); \\\n+ TEST_EXP(hf, h, 2049, raw_hf((_Float16)2048)); /* rounds DOWN */ \\\n+ TEST_EXP(hf, h, 2051, raw_hf((_Float16)2052)); /* rounds UP */ \\\n+})\n+\n+DEF_TEST_VCONV(sf, w, { \\\n+ TEST_EXP(sf, w, 0, SF_zero); \\\n+ TEST_EXP(sf, w, 2, SF_two); \\\n+ TEST_EXP(sf, w, -2, SF_neg_two); \\\n+ TEST_EXP(sf, w, 16777217, raw_sf((float)16777216)); /* rounds DOWN */ \\\n+ TEST_EXP(sf, w, 16777219, raw_sf((float)16777220)); /* rounds UP */ \\\n+})\n+\n+int main(void)\n+{\n+ test_vcvt_uh_hf();\n+ test_vcvt_h_hf();\n+ test_vcvt_ub_hf();\n+ test_vcvt_b_hf();\n+ test_vconv_w_sf();\n+ test_vconv_sf_w();\n+ test_vconv_h_hf();\n+ test_vconv_hf_h();\n+\n+ puts(err ? \"FAIL\" : \"PASS\");\n+ return err ? 1 : 0;\n+}\ndiff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target\nindex afd3dd6d19..1abc5f2124 100644\n--- a/tests/tcg/hexagon/Makefile.target\n+++ b/tests/tcg/hexagon/Makefile.target\n@@ -51,6 +51,7 @@ HEX_TESTS += scatter_gather\n HEX_TESTS += hvx_misc\n HEX_TESTS += hvx_histogram\n HEX_TESTS += fp_hvx\n+HEX_TESTS += fp_hvx_cvt\n HEX_TESTS += fp_hvx_disabled\n HEX_TESTS += invalid-slots\n HEX_TESTS += invalid-encoding\n@@ -132,6 +133,8 @@ fp_hvx: fp_hvx.c hvx_misc.h hex_test.h\n fp_hvx: CFLAGS += -mhvx -mhvx-ieee-fp\n fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h\n fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n+fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h hex_test.h\n+fp_hvx_cvt: CFLAGS += -mhvx -mhvx-ieee-fp\n \n run-fp_hvx_disabled: QEMU_OPTS += -cpu v73,ieee-fp=false\n \n", "prefixes": [ "v4", "14/16" ] }