Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2222051/?format=api
{ "id": 2222051, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222051/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/d408ee2b2c7004e7241aa2beaa136c2f28c73985.1775843299.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<d408ee2b2c7004e7241aa2beaa136c2f28c73985.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "date": "2026-04-10T17:55:59", "name": "[v4,11/16] target/hexagon: add v73 HVX IEEE bfloat16 insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "103b89db2a64985a12bcb5798fe1ceed3de209f2", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/1.1/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/d408ee2b2c7004e7241aa2beaa136c2f28c73985.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 499491, "url": "http://patchwork.ozlabs.org/api/1.1/series/499491/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491", "date": "2026-04-10T17:55:50", "name": "hexagon: add missing HVX float instructions", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499491/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222051/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222051/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=CQE/Nzt0;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=OqZljLh0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fskzd605nz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 11 Apr 2026 03:57:49 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wBG65-0006uS-SI; Fri, 10 Apr 2026 13:56:50 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <matheus.bernardino@oss.qualcomm.com>)\n id 1wBG5y-0006u0-66\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:42 -0400", "from mx0a-0031df01.pphosted.com ([205.220.168.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <matheus.bernardino@oss.qualcomm.com>)\n id 1wBG5v-0001ft-UW\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:41 -0400", "from pps.filterd (m0279867.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63AB13LJ438888\n for <qemu-devel@nongnu.org>; Fri, 10 Apr 2026 17:56:20 GMT", "from mail-dl1-f69.google.com (mail-dl1-f69.google.com\n [74.125.82.69])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deyy9s9uq-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <qemu-devel@nongnu.org>; Fri, 10 Apr 2026 17:56:20 +0000 (GMT)", "by mail-dl1-f69.google.com with SMTP id\n a92af1059eb24-1275c6fc58aso2785951c88.0\n for <qemu-devel@nongnu.org>; Fri, 10 Apr 2026 10:56:20 -0700 (PDT)", "from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n a92af1059eb24-12c3459f7ffsm4256271c88.3.2026.04.10.10.56.18\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 10 Apr 2026 10:56:18 -0700 (PDT)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=GGG/Zp81i+Z\n 5zJgP834y0mXGrz5J69B+j8Rbi2MoPwg=; b=CQE/Nzt0hwSgJ7FulVAuYlcz7I1\n P3tKthbLd+hYwzWe6gX/X86hgtEW9XD5XIH1Wb8Zv4aNcHeVWmLqwfEI5h2rgFON\n AKcGyJpnjXsyIEsy9wUk66094VthEfgjHseAFzeNb4t/90SXVi/wke4CR2zaJI1D\n aJTAWhKUlBTNuES+PlYMlnbezSUxhK+pPVjjc/Nxyjtt4MFEVnOTDoyobopz6Yv6\n Dp6pK8/I4Hs/8x/hKJBf+aiDmu/Ff9pIQKX9Vhbjbc53nEPBoR0z46JdF9Xc6eVE\n 9ZpNrlzxfed7soj3sljWK2q+92ycNNsEN3+Jj2DWIwuJvCzCtotrzTro0SA==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775843780; x=1776448580; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=GGG/Zp81i+Z5zJgP834y0mXGrz5J69B+j8Rbi2MoPwg=;\n b=OqZljLh0cLrWyD3EPtPgZAm8n0/KTltmxy0Qr7zFcph2TPET+doxA9+CRNMfzgcYQ6\n E9Wyz20cpSZh73XFeUO6DBPVmMuuS1hNW1FZvGMVliz/LrPC8U77rOPpNQ2xrfYRyd2s\n A6HarKTgZS02k7NKqKlWbPEpJxevzipEHdU887/xD11GiafAtNWrPQuJQhYbstT/FtPw\n J5yYZzcbuXcRDHQrQWn0ENI8rc13/o8djTbzLMxsxk0tUgQRgxKAQE+NuYxkRgoPdm7R\n T0lQEoyeiaVe1Ye0mtUO0ZoK2+HB3s/SBzDlSeuPMj4eS+guVp8p18RBaxDrgP7MCn/E\n KaOA==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775843780; x=1776448580;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=GGG/Zp81i+Z5zJgP834y0mXGrz5J69B+j8Rbi2MoPwg=;\n b=CuFI1aMeGHditRVq/AL5m3AXRtytbR+vZYg+SGxv74hKlU7wyZLyGXRGwMsHFhg/TU\n KWgDe6fkLlVgIritRjmdRZoxCqLfsxhXDEPuju88jjCcHw3+2yBaS7H/XH7OZsncPfcF\n gnjw4O8aAIhQy8AX4OVlzpJSEYEhY1fwnADSlJpuYhzkP3eqNgw2Uz5/AID2wNWqKV1I\n RjxVr2o57crU5ONJqCMh0H665wUIS9Bf8B563f8EUF4poMgXiOJXAbMt2BxByq2lH8p8\n tgYzsGBv28I0FBHhideFakQT8l2+092fRNe105mVZktVkPed+7COdG8C2WmAsbAD1/ZF\n xjaw==", "X-Gm-Message-State": "AOJu0YyHcNfGVYO3yItpx4g0ovQXU8BgIIhvG8hVzrAhhwElL6ap+EKo\n dz2W4grm5BgH7VtZyU4Pd7Wl93wbGIZlur9NWzF4flrdOdO1OVlRTbdpwFScXqCEEqH12NmnB/C\n 6apqT+mWaVx/hlMOgSes2c0VJIlq4tpKNFAgcjRVJFlHCXxVKuzQ8ECtAPJzo3371ZvHb", "X-Gm-Gg": "AeBDiesqB4LjvsBdYXsRZ31TXZF2RP3R+vaD8a8c5TLG9VVKSM7Lsi2KYfPy2oergSD\n Gsdk7naS8quU+scxcgDaD9OtDwMKUO1I/OCUNd4YZzHRyGxCDmxTgwBbVzSPkWHqoKgw/rqxFSs\n VXBNx55yb4+yL4kcvdL3PALDJe0Iw009YMy25Lfn/uu0wSPjQxd4BF+597ed22XYNVzks0qIG1D\n +NxiRVoS2yc1xTYTa8aLaALXq/tZKN5e2S64gAfW1kffnBkUSNxiL0hye9pZZdIW5zqK1n6DPth\n CtabD4sIyyPC1LiLMGb4cw2MPZ61HvD72pvyoSsCliLiBjLphmLh7Rl0Se8cjf/6mq+7WX2V+wq\n /LqkGyvmxRSINTqWzzJlnXwsAm/r8mFWp+xWqGB6rJD/eretVp+r0TwC7dDagT+7P87uIkGZM18\n izhzllvs1K", "X-Received": [ "by 2002:a05:7022:439f:b0:128:d715:b717 with SMTP id\n a92af1059eb24-12c34e92e3emr2185479c88.13.1775843779479;\n Fri, 10 Apr 2026 10:56:19 -0700 (PDT)", "by 2002:a05:7022:439f:b0:128:d715:b717 with SMTP id\n a92af1059eb24-12c34e92e3emr2185454c88.13.1775843778626;\n Fri, 10 Apr 2026 10:56:18 -0700 (PDT)" ], "From": "Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v4 11/16] target/hexagon: add v73 HVX IEEE bfloat16 insns", "Date": "Fri, 10 Apr 2026 10:55:59 -0700", "Message-Id": "\n <d408ee2b2c7004e7241aa2beaa136c2f28c73985.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775843299.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDEwMDE2OCBTYWx0ZWRfXxTsHZSRagRO+\n Mhl/gbGyCMovlesPRH6TUF0+WVjvdmqGYWFqp/8Mj1bUXGr4RO+CFIReuguUKWowc6Ox0Yt8msI\n MDtMxpliMqy+tA4+960L8mmrQTPIOfyBvQ9JBSk28QJsAHeFGl+MRUrU6pJP3mnHvEGEL0oMaHe\n XYmw/pHqgrFlWXNq/8CW99F4CJFiqkn6M+BFLbffCAc5uAags4ApAR3BcFpz+YOmWTMYuag6b8V\n JkkMInP3QEU9ft2ydQSgjzP17qAlhalFAR4aHDzHxywBABzFDeMOnwKZ7wwFzQkW0DcY76MHLQd\n LRtiPHCHFu/rjRPww6NaIlCEDwFbsk8RsUs3/bJOHcpHCrAhPZMwP3EjbXuMmczWEZkR7UEOAuZ\n UgwJS71fiZbV/d6IbwXC8Tl5eAf5bqCOfwJueoK5tItDkMPdeOcIsY5Ut5OpBPwhY9Ja4ssJ+tI\n QB4t5G0lYrY9XorSf/g==", "X-Proofpoint-GUID": "hE7iTOAI3E5uZBil41gGnUxFC5A0DbeW", "X-Authority-Analysis": "v=2.4 cv=d6fFDxjE c=1 sm=1 tr=0 ts=69d939c4 cx=c_pps\n a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=pGLkceISAAAA:8\n a=EUspDBNiAAAA:8 a=Gs5wSyFCHfQ05zcHo-UA:9 a=vr4QvYf-bLy2KjpDp97w:22", "X-Proofpoint-ORIG-GUID": "hE7iTOAI3E5uZBil41gGnUxFC5A0DbeW", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0\n clxscore=1015 impostorscore=0 adultscore=0 bulkscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100168", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add HVX IEEE bfloat16 (bf16) instructions:\n\nArithmetic operations:\n- V6_vadd_sf_bf, V6_vsub_sf_bf: add/sub bf16 widening to sf output\n- V6_vmpy_sf_bf: multiply bf16 widening to sf output\n- V6_vmpy_sf_bf_acc: multiply-accumulate bf16 widening to sf output\n\nMin/Max operations:\n- V6_vmin_bf, V6_vmax_bf: bf16 min/max\n\nComparison operations:\n- V6_vgtbf: greater-than compare\n- V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor: predicate variants\n\nConversion operations:\n- V6_vcvt_bf_sf: convert sf to bf16\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 37 ++++++++++++\n target/hexagon/mmvec/macros.h | 4 ++\n target/hexagon/mmvec/mmvec.h | 1 +\n target/hexagon/imported/mmvec/encode_ext.def | 15 +++++\n target/hexagon/imported/mmvec/ext.idef | 62 ++++++++++++++++++++\n 5 files changed, 119 insertions(+)", "diff": "diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex 01728121eb..b7e379b089 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -9,8 +9,11 @@\n \n #include \"fpu/softfloat.h\"\n \n+#define FP32_DEF_NAN 0x7FFFFFFF\n+\n #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status)\n #define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status)\n+#define bf16_to_f32(A) bfloat16_to_float32(A, &env->hvx_fp_status)\n \n float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n@@ -29,4 +32,38 @@ int16_t conv_h_hf(float16 a, float_status *fp_status);\n uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status);\n uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status);\n \n+/* IEEE BFloat instructions */\n+\n+#define fp_mult_sf_bf(A, B) \\\n+ float32_mul(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n+\n+#define fp_add_sf_bf(A, B) \\\n+ float32_add(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n+\n+#define fp_sub_sf_bf(A, B) \\\n+ float32_sub(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n+\n+#define fp_mult_sf_bf_acc(f1, f2, f3) \\\n+ float32_muladd(bf16_to_f32(f1), bf16_to_f32(f2), f3, 0, &env->hvx_fp_status)\n+\n+static inline bfloat16 f32_to_bf16(float32 A, float_status *fp_status)\n+{\n+ uint32_t rslt = A;\n+ if ((rslt & 0x1FFFF) == 0x08000) {\n+ /* do not round up if exactly .5 and even already */\n+ } else if ((rslt & 0x8000) == 0x8000) {\n+ rslt += 0x8000; /* rounding to nearest number */\n+ }\n+ rslt = float32_is_any_nan(A) ? FP32_DEF_NAN : rslt;\n+ return float32_to_bfloat16(rslt, fp_status);\n+}\n+\n+#define fp_min_bf(A, B) \\\n+ f32_to_bf16(float32_min(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status), \\\n+ &env->hvx_fp_status);\n+\n+#define fp_max_bf(A, B) \\\n+ f32_to_bf16(float32_max(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status), \\\n+ &env->hvx_fp_status);\n+\n #endif\ndiff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h\nindex 318d44efb7..4945a61194 100644\n--- a/target/hexagon/mmvec/macros.h\n+++ b/target/hexagon/mmvec/macros.h\n@@ -25,6 +25,9 @@\n #include \"accel/tcg/probe.h\"\n #include \"mmvec/hvx_ieee_fp.h\"\n \n+#define fBFLOAT()\n+#define fCVI_VX_NO_TMP_LD()\n+\n #ifndef QEMU_GENERATE\n #define VdV (*(MMVector *restrict)(VdV_void))\n #define VsV (*(MMVector *restrict)(VsV_void))\n@@ -358,5 +361,6 @@\n \n #define fCMPGT_SF(A, B) cmpgt_sf(A, B, &env->hvx_fp_status)\n #define fCMPGT_HF(A, B) cmpgt_hf(A, B, &env->hvx_fp_status)\n+#define fCMPGT_BF(A, B) fCMPGT_SF((uint32_t)(A) << 16, (uint32_t)(B) << 16)\n \n #endif\ndiff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h\nindex 31909303b5..ab991471b1 100644\n--- a/target/hexagon/mmvec/mmvec.h\n+++ b/target/hexagon/mmvec/mmvec.h\n@@ -40,6 +40,7 @@ typedef union {\n int8_t b[MAX_VEC_SIZE_BYTES / 1];\n float32 sf[MAX_VEC_SIZE_BYTES / 4];\n float16 hf[MAX_VEC_SIZE_BYTES / 2];\n+ bfloat16 bf[MAX_VEC_SIZE_BYTES / 2];\n } MMVector;\n \n typedef union {\ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 3572e4de4c..16f043b77d 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -868,4 +868,19 @@ DEF_ENC(V6_vgthf_or,\"00011100100vvvvvPP1uuuuu001101xx\")\n DEF_ENC(V6_vgtsf_xor,\"00011100100vvvvvPP1uuuuu111010xx\")\n DEF_ENC(V6_vgthf_xor,\"00011100100vvvvvPP1uuuuu111011xx\")\n \n+/* BFLOAT instructions */\n+DEF_ENC(V6_vmpy_sf_bf,\"00011101010vvvvvPP1uuuuu100ddddd\")\n+DEF_ENC(V6_vmpy_sf_bf_acc,\"00011101000vvvvvPP1uuuuu000xxxxx\")\n+DEF_ENC(V6_vadd_sf_bf,\"00011101010vvvvvPP1uuuuu110ddddd\")\n+DEF_ENC(V6_vsub_sf_bf,\"00011101010vvvvvPP1uuuuu101ddddd\")\n+DEF_ENC(V6_vmax_bf,\"00011101010vvvvvPP1uuuuu111ddddd\")\n+DEF_ENC(V6_vmin_bf,\"00011101010vvvvvPP1uuuuu000ddddd\")\n+DEF_ENC(V6_vcvt_bf_sf,\"00011101010vvvvvPP1uuuuu011ddddd\")\n+\n+/* BFLOAT compare instructions */\n+DEF_ENC(V6_vgtbf,\"00011100100vvvvvPP1uuuuu011110dd\")\n+DEF_ENC(V6_vgtbf_and,\"00011100100vvvvvPP1uuuuu110100xx\")\n+DEF_ENC(V6_vgtbf_or,\"00011100100vvvvvPP1uuuuu001110xx\")\n+DEF_ENC(V6_vgtbf_xor,\"00011100100vvvvvPP1uuuuu111100xx\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex a7043d598c..44135a8eea 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -3163,6 +3163,15 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n } \\\n }\n \n+#define VCMPGT_BF(DEST, ASRC, ASRCOP, CMP, N, SRC, MASK, WIDTH) \\\n+{ \\\n+ fBFLOAT(); \\\n+ for (fHIDE(int) i = 0; i < fVBYTES(); i += WIDTH) { \\\n+ fHIDE(int) VAL = fCMPGT_BF(VuV.SRC[i/WIDTH],VvV.SRC[i/WIDTH]) ? MASK : 0; \\\n+ fSETQBITS(DEST,WIDTH,MASK,i,ASRC ASRCOP VAL); \\\n+ } \\\n+}\n+\n /* Vector SF compare */\n #define MMVEC_CMPGT_SF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \\\n EXTINSN(V6_vgt##TYPE##_and, \"Qx4&=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n@@ -3201,8 +3210,61 @@ ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n DESCR\" greater than\", \\\n VCMPGT_HF(QdV, , , \">\", N, SRC, MASK, WIDTH))\n \n+/* Vector BF compare */\n+#define MMVEC_CMPGT_BF(TYPE,TYPE2,DESCR,N,MASK,WIDTH,SRC) \\\n+ EXTINSN(V6_vgt##TYPE##_and, \"Qx4&=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\",\\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-and\", \\\n+ VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), &, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_xor, \"Qx4^=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-xor\", \\\n+ VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), ^, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE##_or, \"Qx4|=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than with predicate-or\", \\\n+ VCMPGT_BF(QxV, fGETQBITS(QxV,WIDTH,MASK,i), |, \">\", N, SRC, MASK, WIDTH)) \\\n+ EXTINSN(V6_vgt##TYPE, \"Qd4=vcmp.gt(Vu32.\" TYPE2 \",Vv32.\" TYPE2 \")\", \\\n+ ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+ DESCR\" greater than\", \\\n+ VCMPGT_BF(QdV, , , \">\", N, SRC, MASK, WIDTH))\n+\n MMVEC_CMPGT_SF(sf,\"sf\",\"Vector sf Compare \", fVELEM(32), 0xF, 4, sf)\n MMVEC_CMPGT_HF(hf,\"hf\",\"Vector hf Compare \", fVELEM(16), 0x3, 2, hf)\n+MMVEC_CMPGT_BF(bf,\"bf\",\"Vector bf Compare \", fVELEM(16), 0x3, 2, bf)\n+\n+/******************************************************************************\n+ BFloat arithmetic and max/min instructions\n+ ******************************************************************************/\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_bf,\n+ \"Vdd32.sf=vadd(Vu32.bf,Vv32.bf)\", \"Vector IEEE add: bf widen to sf\",\n+ VddV.v[0].sf[i] = fp_add_sf_bf(VuV.bf[2*i], VvV.bf[2*i]);\n+ VddV.v[1].sf[i] = fp_add_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_bf,\n+ \"Vdd32.sf=vsub(Vu32.bf,Vv32.bf)\", \"Vector IEEE sub: bf widen to sf\",\n+ VddV.v[0].sf[i] = fp_sub_sf_bf(VuV.bf[2*i], VvV.bf[2*i]);\n+ VddV.v[1].sf[i] = fp_sub_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf,\n+ \"Vdd32.sf=vmpy(Vu32.bf,Vv32.bf)\", \"Vector IEEE mul: hf widen to sf\",\n+ VddV.v[0].sf[i] = fp_mult_sf_bf(VuV.bf[2*i], VvV.bf[2*i]);\n+ VddV.v[1].sf[i] = fp_mult_sf_bf(VuV.bf[2*i+1], VvV.bf[2*i+1]); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_bf_acc,\n+ \"Vxx32.sf+=vmpy(Vu32.bf,Vv32.bf)\", \"Vector IEEE fma: hf widen to sf\",\n+ VxxV.v[0].sf[i] = fp_mult_sf_bf_acc(VuV.bf[2*i], VvV.bf[2*i], VxxV.v[0].sf[i]);\n+ VxxV.v[1].sf[i] = fp_mult_sf_bf_acc(VuV.bf[2*i+1], VvV.bf[2*i+1], VxxV.v[1].sf[i]);\n+ fCVI_VX_NO_TMP_LD(); fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_16(32, vcvt_bf_sf,\n+ \"Vd32.bf=vcvt(Vu32.sf,Vv32.sf)\", \"Vector IEEE cvt: sf to bf\",\n+ VdV.bf[2*i] = f32_to_bf16(VuV.sf[i], &env->hvx_fp_status);\n+ VdV.bf[2*i+1] = f32_to_bf16(VvV.sf[i], &env->hvx_fp_status); fBFLOAT())\n+\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmax_bf, \"Vd32.bf=vmax(Vu32.bf,Vv32.bf)\",\n+ \"Vector IEEE max: bf\", VdV.bf[i] = fp_max_bf(VuV.bf[i], VvV.bf[i]);\n+ fBFLOAT())\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, \"Vd32.bf=vmin(Vu32.bf,Vv32.bf)\",\n+ \"Vector IEEE max: bf\", VdV.bf[i] = fp_min_bf(VuV.bf[i], VvV.bf[i]);\n+ fBFLOAT())\n \n /******************************************************************************\n DEBUG Vector/Register Printing\n", "prefixes": [ "v4", "11/16" ] }