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GET /api/1.1/patches/2222009/?format=api
{ "id": 2222009, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222009/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260410150553.156795-4-muhammad.kamran@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260410150553.156795-4-muhammad.kamran@arm.com>", "date": "2026-04-10T15:05:53", "name": "[v4,3/3] aarch64: add usubc<m>5 expansion pattern to machine description", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c71b5ad44929ce1764eb3345b4bf3fef2d58287b", "submitter": { "id": 92852, "url": "http://patchwork.ozlabs.org/api/1.1/people/92852/?format=api", "name": "Muhammad Kamran", "email": "muhammad.kamran@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260410150553.156795-4-muhammad.kamran@arm.com/mbox/", "series": [ { "id": 499479, "url": "http://patchwork.ozlabs.org/api/1.1/series/499479/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=499479", "date": "2026-04-10T15:05:50", "name": "aarch64: Implement uaddc/usubc expansion and carry/borrow round-trip cleanup", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499479/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222009/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222009/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=R6/6piQD;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=R6/6piQD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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helo=nebula.arm.com; pr=C" ], "From": "Muhammad Kamran <muhammad.kamran@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Richard Earnshaw <richard.earnshaw@arm.com>, Tamar Christina\n <tamar.christina@arm.com>, Kyrylo Tkachov <ktkachov@nvidia.com>, \"Alice\n Carlotti\" <alice.carlotti@arm.com>, Alex Coplan <alex.coplan@arm.com>,\n \"Andrew Pinski\" <andrew.pinski@oss.qualcomm.com>, Wilco Dijkstra\n <wilco.dijkstra@arm.com>, Muhammad Kamran <muhammad.kamran@arm.com>", "Subject": "[PATCH v4 3/3] aarch64: add usubc<m>5 expansion pattern to machine\n description", "Date": "Fri, 10 Apr 2026 15:05:53 +0000", "Message-ID": "<20260410150553.156795-4-muhammad.kamran@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260410150553.156795-1-muhammad.kamran@arm.com>", "References": "<20260410150553.156795-1-muhammad.kamran@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n AM4PEPF00027A67:EE_|GV1PR08MB10403:EE_|AM3PEPF00009B9C:EE_|AS1PR08MB7428:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2eab4797-526e-465d-85ec-08de9712e2b6", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|82310400026|36860700016|1800799024|376014|56012099003|13003099007|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info-Original": "\n GbWDzgCtW5jH4tOONJTYLR8JZQW21AB3tDMCsQtShF/TZchB0A+O3UAQusJ3hIjWn6dWw9tEJ/yAj38smIZvymxtpuly/fn8IfChl2HcBoH5Hz1CGFSFwGHnZUlKjcKsClMLmewYlNgaySmFG2H5Fh6e1Oz20IoU+nOw661T0iB0HmmlZY0UfLpPGT6fBDq/2lgeMbpZ20YPh1Fb4FnLM3up4mjYdmeZHzjxu2R/dx0YKuMSrzPiBB8WWpXsr6u8SJg1RS0tWCKhPG2iSfeAXeYFy99h2mLh5ouvOC+UewGxC6ZAeDcvm8JqBu57nC8H4HHK+zNnZWCMyH2Q+a33XOHfghw+OUo49ZAC4LRSQhGeE9U7yMvS5mJ3WgSPjV5bFwieJIe1OEBEzwNZnEJ+6C+fIDUa9hVwDCz6VroFTHM3hyiOSCSWMt22i/cAVafzjt+wpQnpWpz6RZRyUZDrObdO8IP7JDpHIyqkRZ24jMw/Bwoj7Hx3938fuW1BQjMTYNdtgsdevl0CLPU6phMAkVKM4K7xmfT24L4shooxFQrqzwP9mNM19ONun0Vd9r3bMEH41tLeSNk/J1/S8xCSK0VI/w5+PLO+Ip8yRtt7Dnc45k4vxZ9C35NSylP/aBlb+DsgS3K4njrzHyNg4sQTEBW4x1pGK9lDBxA8tfnJ9377rcyvaA1pnyCd+TjAKzuW23x+KSWHAudaLN21KX+DMe8PXdAtY6gYvtidc3YNlkY=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM3PEPF00009B9C.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "The pattern expands usubc(diff, Bout, x, y, Bin into:\nnegs Bin\nsbcs diff, x, y\ncset Bout, cc\n\nIt also tries to fold if y, or Bin are constants:\n\nIf Bin != 0, Y = ~0:\nmov diff, x\nmov Bout, 1\n\nIf Bin = 0, Y = 0:\nmov diff, x\nmov Bout, 0\n\nSimilar to the chained uaddc, chained usubc expansions results in a round trip\nCC -> register -> CC. Remove that round-trip as CSET-like materialization does\nnot clobber flags, so CC already carries the same bit.\n\ngcc/ChangeLog:\n\n\tPR target/122525\n\t* config/aarch64/aarch64.md\n\t(usubc<mode>5): Expansion pattern for usubc<m>5.\n\t(*aarch64_setc_from_borrow_<mode>) Post-combine no-op split\n\tpattern for carry chain elimination.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/usubc-builtin-sub-overflow.c: New test\n\tchained usubc expansion for __builtin_usubc_overflow.\n\t* gcc.target/aarch64/usubc-builtin-subc.c: New test for\n\t__builtin_subc.\n\t* gcc.target/aarch64/usubc-builtin-subcl.c: New test for\n\t__builtin_subcl.\n\t* gcc.target/aarch64/usubc-const-minus1.c: New test for\n\tusubc where y = ~0.\n\t* gcc.target/aarch64/usubc-const-plus1.c: New test for\n\tusubc where y is constant.\n---\n gcc/config/aarch64/aarch64.md | 89 +++++++++++++++++++\n .../aarch64/usubc-builtin-sub-overflow.c | 28 ++++++\n .../gcc.target/aarch64/usubc-builtin-subc.c | 17 ++++\n .../gcc.target/aarch64/usubc-builtin-subcl.c | 17 ++++\n .../gcc.target/aarch64/usubc-const-minus1.c | 14 +++\n .../gcc.target/aarch64/usubc-const-plus1.c | 12 +++\n 6 files changed, 177 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c", "diff": "diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 3fd476f838f..75aa4e893c6 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -4111,6 +4111,95 @@ (define_insn \"*subsi3_carryin_alt_uxtw\"\n [(set_attr \"type\" \"adc_reg\")]\n )\n \n+(define_expand \"usubc<mode>5\"\n+ [(match_operand:GPI 0 \"register_operand\") ;; difference\n+ (match_operand:GPI 1 \"register_operand\") ;; borrow-out\n+ (match_operand:GPI 2 \"register_operand\") ;; x\n+ (match_operand:GPI 3 \"nonmemory_operand\") ;; y\n+ (match_operand:GPI 4 \"nonmemory_operand\")] ;; borrow-in\n+ \"\"\n+{\n+ if (operands[4] == const0_rtx)\n+ {\n+ rtx y = operands[3];\n+ if (aarch64_reg_or_zero (y, <MODE>mode))\n+\temit_insn (gen_sub<mode>3_compare1 (operands[0], operands[2], y));\n+ else if (CONST_SCALAR_INT_P (y) && aarch64_plus_immediate (y, <MODE>mode))\n+\t{\n+\t rtx minus_y = immed_wide_int_const (wi::neg (\n+\t\t\t\t\t rtx_mode_t (y, <MODE>mode)),\n+\t\t\t\t\t <MODE>mode);\n+\t emit_insn (gen_sub<mode>3_compare1_imm (operands[0], operands[2],\n+\t\t\t\t\t\t y, minus_y));\n+\t}\n+ else\n+\t{\n+\t y = force_reg (<MODE>mode, y);\n+\t emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[2], y));\n+\t}\n+ }\n+ else if (CONST_SCALAR_INT_P (operands[4]))\n+ {\n+ if (operands[3] == constm1_rtx)\n+\t{\n+\t emit_move_insn (operands[0], operands[2]);\n+\t emit_move_insn (operands[1], const1_rtx);\n+\t DONE;\n+\t}\n+ else\n+\t{\n+\t rtx rhs = plus_constant (<MODE>mode, operands[3], 1);\n+\t if (aarch64_reg_or_zero (rhs, <MODE>mode))\n+\t emit_insn (gen_sub<mode>3_compare1 (operands[0], operands[2], rhs));\n+\t else if (CONST_SCALAR_INT_P (rhs)\n+\t\t && aarch64_plus_immediate (rhs, <MODE>mode))\n+\t {\n+\t rtx minus_rhs\n+\t\t= immed_wide_int_const (wi::neg (rtx_mode_t (rhs, <MODE>mode)),\n+\t\t\t\t\t<MODE>mode);\n+\t emit_insn (gen_sub<mode>3_compare1_imm (operands[0], operands[2],\n+\t\t\t\t\t\t rhs, minus_rhs));\n+\t }\n+\t else\n+\t {\n+\t rhs = force_reg (<MODE>mode, rhs);\n+\t emit_insn (gen_sub<mode>3_compare1 (operands[0],\n+\t\t\t\t\t\t operands[2],\n+\t\t\t\t\t\t rhs));\n+\t }\n+\t}\n+ }\n+ else\n+ {\n+ rtx cin = force_reg (<MODE>mode, operands[4]);\n+ rtx tmp = gen_reg_rtx (<MODE>mode);\n+ rtx y = operands[3];\n+ if (!register_operand (y, <MODE>mode))\n+\ty = force_reg (<MODE>mode, y);\n+ emit_insn (gen_sub<mode>3_compare1 (tmp, const0_rtx, cin));\n+ emit_insn (gen_usub<mode>3_carryinC (operands[0], operands[2],\n+\t\t\t\t\t y));\n+ }\n+ rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+ rtx pat = gen_rtx_GEU (<MODE>mode, cc, const0_rtx);\n+ emit_insn (gen_rtx_SET (operands[1], pat));\n+ DONE;\n+})\n+\n+;; Similar to the chained uaddc, chained usubc expansions results in a round\n+;; trip CC -> register -> CC. Remove that round-trip as CSET-like\n+;; materialization does not clobber flags, so CC already carries the same bit.\n+(define_insn_and_split \"*aarch64_setc_from_borrow_<mode>\"\n+ [(set (reg:CC CC_REGNUM)\n+\t(compare:CC\n+\t (const_int 0)\n+\t (match_operand:GPI 0 \"aarch64_borrow_operation\" \"\")))]\n+ \"\"\n+ \"#\"\n+ \"\"\n+ [(const_int 0)]\n+ \"emit_note (NOTE_INSN_DELETED); DONE;\")\n+\n (define_expand \"usub<GPI:mode>3_carryinC\"\n [(parallel\n [(set (reg:CC CC_REGNUM)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c\nnew file mode 100644\nindex 00000000000..2e4b7c311d3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-sub-overflow.c\n@@ -0,0 +1,28 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+static unsigned long\n+usubc (unsigned long x, unsigned long y, unsigned long carry_in,\n+ unsigned long *carry_out)\n+{\n+ unsigned long r;\n+ unsigned long c1 = __builtin_sub_overflow (x, y, &r);\n+ unsigned long c2 = __builtin_sub_overflow (r, carry_in, &r);\n+ *carry_out = c1 + c2;\n+ return r;\n+}\n+\n+void __attribute__ ((__noinline__))\n+bar (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = usubc (p[0], q[0], 0, &c);\n+ p[1] = usubc (p[1], q[1], c, &c);\n+ p[2] = usubc (p[2], q[2], c, &c);\n+ p[3] = usubc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"sbcs\\\\t\\[xw\\]\\[0-9\\]+, \\[xw\\]\\[0-9\\]+,\n+ * \\[xw\\]\\[0-9\\]+\" 3 } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\\[xw\\]\\[0-9\\]+, cc+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c\nnew file mode 100644\nindex 00000000000..6279aa3fd83\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subc.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+bar (unsigned int *p, unsigned int *q)\n+{\n+ unsigned int c;\n+ p[0] = __builtin_subc (p[0], q[0], 0, &c);\n+ p[1] = __builtin_subc (p[1], q[1], c, &c);\n+ p[2] = __builtin_subc (p[2], q[2], c, &c);\n+ p[3] = __builtin_subc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"sbcs\\\\tw\\[0-9\\]+, w\\[0-9\\]+, w\\[0-9\\]+\" 3\n+ * } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tw\\[0-9\\]+, cc+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c\nnew file mode 100644\nindex 00000000000..4792afba4f0\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-builtin-subcl.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+bar (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = __builtin_subcl (p[0], q[0], 0, &c);\n+ p[1] = __builtin_subcl (p[1], q[1], c, &c);\n+ p[2] = __builtin_subcl (p[2], q[2], c, &c);\n+ p[3] = __builtin_subcl (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"sbcs\\\\tx\\[0-9\\]+, x\\[0-9\\]+,\n+ * x\\[0-9\\]+\" 3 } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tx\\[0-9\\]+, cc+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c b/gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c\nnew file mode 100644\nindex 00000000000..0c9f94bb97d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-const-minus1.c\n@@ -0,0 +1,14 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+bar (unsigned long x, unsigned long *b)\n+{\n+ return __builtin_subcl (x, ~0UL, 1, b);\n+}\n+\n+/* { dg-final { scan-assembler-not \"subs\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"sbcs\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\" } } */\n+/* { dg-final { scan-assembler \"mov\\\\tx\\[0-9\\]+, 1\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c b/gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c\nnew file mode 100644\nindex 00000000000..d82a9ef6216\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/usubc-const-plus1.c\n@@ -0,0 +1,12 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+bar (unsigned long x, unsigned long *b)\n+{\n+ return __builtin_subcl (x, 41, 1, b);\n+}\n+\n+/* { dg-final { scan-assembler \"subs\\\\tx\\[0-9\\]+, x\\[0-9\\]+, 42\" } } */\n+/* { dg-final { scan-assembler-not \"sbcs\\\\t\" } } */\n", "prefixes": [ "v4", "3/3" ] }