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GET /api/1.1/patches/2222008/?format=api
{ "id": 2222008, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2222008/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260410150553.156795-3-muhammad.kamran@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260410150553.156795-3-muhammad.kamran@arm.com>", "date": "2026-04-10T15:05:52", "name": "[v4,2/3] aarch64: add uaddc<m>5 expansion pattern to machine description", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "670d2ce293f3ea1a591c0eafca8fc398e6d09847", "submitter": { "id": 92852, "url": "http://patchwork.ozlabs.org/api/1.1/people/92852/?format=api", "name": "Muhammad Kamran", "email": "muhammad.kamran@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260410150553.156795-3-muhammad.kamran@arm.com/mbox/", "series": [ { "id": 499479, "url": "http://patchwork.ozlabs.org/api/1.1/series/499479/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=499479", "date": "2026-04-10T15:05:50", "name": "aarch64: Implement uaddc/usubc expansion and carry/borrow round-trip cleanup", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499479/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222008/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222008/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=selector1 header.b=T8IbPFdx;\n\tdkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com\n header.a=rsa-sha256 header.s=selector1 header.b=T8IbPFdx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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helo=nebula.arm.com; pr=C" ], "From": "Muhammad Kamran <muhammad.kamran@arm.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Richard Earnshaw <richard.earnshaw@arm.com>, Tamar Christina\n <tamar.christina@arm.com>, Kyrylo Tkachov <ktkachov@nvidia.com>, \"Alice\n Carlotti\" <alice.carlotti@arm.com>, Alex Coplan <alex.coplan@arm.com>,\n \"Andrew Pinski\" <andrew.pinski@oss.qualcomm.com>, Wilco Dijkstra\n <wilco.dijkstra@arm.com>, Muhammad Kamran <muhammad.kamran@arm.com>", "Subject": "[PATCH v4 2/3] aarch64: add uaddc<m>5 expansion pattern to machine\n description", "Date": "Fri, 10 Apr 2026 15:05:52 +0000", "Message-ID": "<20260410150553.156795-3-muhammad.kamran@arm.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260410150553.156795-1-muhammad.kamran@arm.com>", "References": "<20260410150553.156795-1-muhammad.kamran@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "1", "X-MS-TrafficTypeDiagnostic": "\n AM4PEPF00027A65:EE_|VE1PR08MB5615:EE_|DB3PEPF00008859:EE_|GVXPR08MB11471:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a1a5f7bd-e9de-49a5-0ec1-08de9712e09e", "x-checkrecipientrouted": "true", "NoDisclaimer": "true", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam-Untrusted": "BCL:0;\n ARA:13230040|376014|82310400026|1800799024|36860700016|13003099007|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info-Original": "\n u875xOmj2wwSDkhTQb04nFtkIaqPh3nQE56ihbhjFx61+UST6C/YBDRFui4y5/VXzzDY7vcrE/IXNxR8WDoJ7ctf33sKRKPrG7pzytyLBJqvSwrNCRWodIed2L4zI+0rxb/KW7yEm3WYFE4JbG9NM+yzxRoBWF4LUuXD3RYdBR/YJEfiH8FxX3JWPYUBRX/WRLGO2mrOpzblQdidzEtLgJbKKOCd1r9g1AjXkBufHNj0qKPvKypWaw6RPTxZk50dMY39SJYeXTHw9r9dw4Pq8K7grpya0CVz+jEtUcodKy95AXprR0xqHgf+8GHBytOD5L5QBaDOESAOg13MCAURkJypiiV1Tpeu+qXGeX3oQnCwlZ8+A9UGQfL8phk+IHFI8mfarSM+RoEv/CdctNYMF8AnvszQtOrBiZeXvPfd6FsI5uAAbbqH/Ps6ywyUof9B5Ullf+kbO7ftqu6Zzq2VB/R8cC9AliENEKMrlwzAQT6YeU+8yQPLMVaP5wFccPvkvNadh+/z6WkaDWbin79jdCAxhefHE/gDGrKhHhnY0PGLbPUUla22xToB1zfWe8wLaCUrAIrhxFiLXTL0Eu2LOEHCGoSyOV11O9GSopXjr/vLf7YUG+16W5gduES7Cb8/czsfwcnGnqZ7vHg1kktn+N2KEnAxlSruZ5/LZlJLnBfakIjsvyFOv4k9sZAJOkmfPoWVP1Oye+PRmkkYrULdyRyh4Zt27+candKpkbky1cY=", "X-Forefront-Antispam-Report-Untrusted": "CIP:172.205.89.229; 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Ip=[4.158.2.129];\n Helo=[outbound-uk1.az.dlp.m.darktrace.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DB3PEPF00008859.eurprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "The pattern expands uaddc(sum, Cout, x, y, Cin) into:\ncmp Cin, #1\nadcs sum, x, y\ncset Cout, cs\n\nThe expansion folds the additions if the operands are known at compile time:\n\nIf Cin = 0, y = 0:\nmov sum, x\nmov Cout, 0\n\nIf Cin != 0, y = ~0:\nmov sum, x\nmov Cout, 1\n\nCarry chained uaddc expansion results in a rount trip CC -> register -> CC.\nRemove that round-trip as CSET-like materialization does not clobber flags, so\nCC already carries the same bit.\n\ngcc/ChangeLog:\n\n\tPR target/122525\n\t* config/aarch64/aarch64.md\n\t(uaddc<mode>5): Expansion pattern for uaddc<m>5.\n\t(*aarch64_setc_from_carry_<mode>) Post-combine no-op split pattern for\n\tcarry chain elimination in CC_Cmode.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/aarch64/uaddc-builtin-add-overflow.c: New test for chained\n\tuaddc expansion for __builtin_add_overflow.\n\t* gcc.target/aarch64/uaddc-builtin-addc.c: New test chained uaddc\n\texpansion for __builtin_addc.\n\t* gcc.target/aarch64/uaddc-builtin-addcl.c: New test for uaddc expansion\n\tfor __builtin_addcl.\n\t* gcc.target/aarch64/uaddc-const-minus1.c: New test for uaddc expansion\n\twhere addend 2 is ~0.\n\t* gcc.target/aarch64/uaddc-const-plus1.c: New test for uaddc expansion\n\twhere addend 2 is a constant.\n---\n gcc/config/aarch64/aarch64.md | 80 +++++++++++++++++++\n .../aarch64/uaddc-builtin-add-overflow.c | 28 +++++++\n .../gcc.target/aarch64/uaddc-builtin-addc.c | 17 ++++\n .../gcc.target/aarch64/uaddc-builtin-addcl.c | 17 ++++\n .../gcc.target/aarch64/uaddc-const-minus1.c | 14 ++++\n .../gcc.target/aarch64/uaddc-const-plus1.c | 12 +++\n 6 files changed, 168 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c\n create mode 100644 gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c", "diff": "diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 744acac0290..3fd476f838f 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -3389,6 +3389,86 @@ (define_insn \"*add<mode>3_carryinC\"\n [(set_attr \"type\" \"adc_reg\")]\n )\n \n+(define_expand \"uaddc<mode>5\"\n+ [(match_operand:GPI 0 \"register_operand\") ;; sum\n+ (match_operand:GPI 1 \"register_operand\") ;; carry-out\n+ (match_operand:GPI 2 \"register_operand\") ;; x\n+ (match_operand:GPI 3 \"nonmemory_operand\") ;; y\n+ (match_operand:GPI 4 \"nonmemory_operand\")] ;; carry-in\n+ \"\"\n+{\n+ if (operands[4] == const0_rtx)\n+ {\n+ if (operands[3] == const0_rtx)\n+\t{\n+\t emit_move_insn (operands[0], operands[2]);\n+\t emit_move_insn (operands[1], const0_rtx);\n+\t}\n+ else\n+\t{\n+\t rtx y = operands[3];\n+\t if (!aarch64_plus_operand (y, <MODE>mode))\n+\t y = force_reg (<MODE>mode, y);\n+\t emit_insn (gen_add<mode>3_compareC (operands[0], operands[2], y));\n+\t rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+\t rtx pat = gen_rtx_LTU (<MODE>mode, cc, const0_rtx);\n+\t emit_insn (gen_rtx_SET (operands[1], pat));\n+\t}\n+ }\n+ else if (CONST_SCALAR_INT_P (operands[4]))\n+ {\n+ if (operands[3] == constm1_rtx)\n+\t{\n+\t emit_move_insn (operands[0], operands[2]);\n+\t emit_move_insn (operands[1], const1_rtx);\n+\t}\n+ else\n+\t{\n+\t rtx rhs = plus_constant (<MODE>mode, operands[3], 1);\n+\t if (!aarch64_plus_operand (rhs, <MODE>mode))\n+\t rhs = force_reg (<MODE>mode, rhs);\n+\t emit_insn (gen_add<mode>3_compareC (operands[0], operands[2], rhs));\n+\t rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+\t rtx pat = gen_rtx_LTU (<MODE>mode, cc, const0_rtx);\n+\t emit_insn (gen_rtx_SET (operands[1], pat));\n+\t}\n+ }\n+ else\n+ {\n+ rtx cin = force_reg (<MODE>mode, operands[4]);\n+ rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM);\n+ rtx adc_cc = gen_rtx_REG (CC_ADCmode, CC_REGNUM);\n+ rtx y = operands[3];\n+ if (!register_operand (y, <MODE>mode))\n+\ty = force_reg (<MODE>mode, y);\n+ rtx cmp = gen_rtx_COMPARE (CC_Cmode,\n+\t\t\t\t gen_rtx_PLUS (<MODE>mode, cin, constm1_rtx),\n+\t\t\t\t cin);\n+ emit_insn (gen_rtx_SET (cc, cmp));\n+ emit_insn (gen_add<mode>3_carryinC (operands[0], operands[2],\n+\t\t\t\t\t y));\n+ rtx pat = gen_rtx_GEU (<MODE>mode, adc_cc, const0_rtx);\n+ emit_insn (gen_rtx_SET (operands[1], pat));\n+ }\n+ DONE;\n+})\n+\n+;; The uaddc expansion results in a round trip CC -> register -> CC. Remove\n+;; that round-trip as CSET-like materialization does not clobber flags, so CC\n+;; already carries the same bit.\n+;; With STORE_FLAG_VALUE == 1, simplify-rtx can canonicalize carry - 1 to\n+;; -!carry, where !carry is the complementary borrow-like test on the same CC.\n+(define_insn_and_split \"*aarch64_setc_from_carry_<mode>\"\n+ [(set (reg:CC_C CC_REGNUM)\n+\t(compare:CC_C\n+\t (neg:GPI (match_operand:GPI 0 \"aarch64_borrow_operation\" \"\"))\n+\t (match_operand:GPI 1 \"aarch64_carry_operation\" \"\")))]\n+ \"rtx_equal_p (XEXP (operands[0], 0), XEXP (operands[1], 0))\"\n+ \"#\"\n+ \"\"\n+ [(const_int 0)]\n+ \"emit_note (NOTE_INSN_DELETED); DONE;\")\n+\n (define_expand \"add<mode>3_carryinV\"\n [(parallel\n [(set (reg:CC_V CC_REGNUM)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c\nnew file mode 100644\nindex 00000000000..ff8301973a8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-add-overflow.c\n@@ -0,0 +1,28 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+static unsigned long\n+uaddc (unsigned long x, unsigned long y, unsigned long carry_in,\n+ unsigned long *carry_out)\n+{\n+ unsigned long r;\n+ unsigned long c1 = __builtin_add_overflow (x, y, &r);\n+ unsigned long c2 = __builtin_add_overflow (r, carry_in, &r);\n+ *carry_out = c1 + c2;\n+ return r;\n+}\n+\n+void\n+foo (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = uaddc (p[0], q[0], 0, &c);\n+ p[1] = uaddc (p[1], q[1], c, &c);\n+ p[2] = uaddc (p[2], q[2], c, &c);\n+ p[3] = uaddc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"adcs\\\\t\\[xw\\]\\[0-9\\]+, \\[xw\\]\\[0-9\\]+,\n+\\[xw\\]\\[0-9\\]+\" 3 } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\\[xw\\]\\[0-9\\]+, cs+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c\nnew file mode 100644\nindex 00000000000..ee28860c105\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addc.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+foo (unsigned int *p, unsigned int *q)\n+{\n+ unsigned int c;\n+ p[0] = __builtin_addc (p[0], q[0], 0, &c);\n+ p[1] = __builtin_addc (p[1], q[1], c, &c);\n+ p[2] = __builtin_addc (p[2], q[2], c, &c);\n+ p[3] = __builtin_addc (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"adcs\\\\tw\\[0-9\\]+, w\\[0-9\\]+, w\\[0-9\\]+\" 3\n+ * } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tw\\[0-9\\]+, cs+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c\nnew file mode 100644\nindex 00000000000..004d950f48c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-builtin-addcl.c\n@@ -0,0 +1,17 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+void\n+foo (unsigned long *p, unsigned long *q)\n+{\n+ unsigned long c;\n+ p[0] = __builtin_addcl (p[0], q[0], 0, &c);\n+ p[1] = __builtin_addcl (p[1], q[1], c, &c);\n+ p[2] = __builtin_addcl (p[2], q[2], c, &c);\n+ p[3] = __builtin_addcl (p[3], q[3], c, &c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"adcs\\\\tx\\[0-9\\]+, x\\[0-9\\]+, x\\[0-9\\]+\" 3\n+ * } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\tx\\[0-9\\]+, cs+.*\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c b/gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c\nnew file mode 100644\nindex 00000000000..48fbd5b8498\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-const-minus1.c\n@@ -0,0 +1,14 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+foo (unsigned long x, unsigned long *c)\n+{\n+ return __builtin_addcl (x, ~0UL, 1, c);\n+}\n+\n+/* { dg-final { scan-assembler-not \"adds\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"adcs\\\\t\" } } */\n+/* { dg-final { scan-assembler-not \"cset\\\\t\" } } */\n+/* { dg-final { scan-assembler \"mov\\\\tx\\[0-9\\]+, 1\" } } */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c b/gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c\nnew file mode 100644\nindex 00000000000..d072f66525d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/uaddc-const-plus1.c\n@@ -0,0 +1,12 @@\n+/* PR target/122525 */\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+\n+unsigned long\n+foo (unsigned long x, unsigned long *c)\n+{\n+ return __builtin_addcl (x, 41, 1, c);\n+}\n+\n+/* { dg-final { scan-assembler \"adds\\\\tx\\[0-9\\]+, x\\[0-9\\]+, #42\" } } */\n+/* { dg-final { scan-assembler-not \"adcs\\\\t\" } } */\n", "prefixes": [ "v4", "2/3" ] }