Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2221939/?format=api
{ "id": 2221939, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221939/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-3-1d184cb5c60a@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260410-sdxi-base-v1-3-1d184cb5c60a@amd.com>", "date": "2026-04-10T13:07:13", "name": "[03/23] dmaengine: sdxi: Add PCI initialization", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "749011cc6114c68b078148c32b4c5c072af71cc3", "submitter": { "id": 91626, "url": "http://patchwork.ozlabs.org/api/1.1/people/91626/?format=api", "name": "Nathan Lynch via B4 Relay", "email": "devnull+nathan.lynch.amd.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260410-sdxi-base-v1-3-1d184cb5c60a@amd.com/mbox/", "series": [ { "id": 499458, "url": "http://patchwork.ozlabs.org/api/1.1/series/499458/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499458", "date": "2026-04-10T13:07:10", "name": "dmaengine: Smart Data Accelerator Interface (SDXI) basic support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499458/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221939/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221939/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52313-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ThL/1M3a;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-52313-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"ThL/1M3a\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fscbK39xKz1yGb\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 23:09:49 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 3B7C33029E6E\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 13:07:52 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 098DC33B6F8;\n\tFri, 10 Apr 2026 13:07:50 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id D3007313E1D;\n\tFri, 10 Apr 2026 13:07:49 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id A6B6BC2BC9E;\n\tFri, 10 Apr 2026 13:07:49 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 9C12BF4485D;\n\tFri, 10 Apr 2026 13:07:49 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775826469; cv=none;\n b=n4zrRF41jhtZbEhthK5aNsi9UHmu6EZCKF+mOubCs49Qv3P+f3iLDsXow63hWcaTYtG4WdnOg8KF6YLL5uZJI39IjQRk+7Bv15BDpNM5wpRgrvn/Xh3bPIxsCnhlRDMSMwfpzKp4a/RhO1if4H8608Z5xq1yEQtdPnXTxPRKbRw=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775826469; c=relaxed/simple;\n\tbh=HKLbyRBVfPTHlCYt6B5t9msTPNnxCYsSjPdFZbFLnuw=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=eAJGJUM+4inkAkZFmcvpZhlAyTS+lx1NMnr8yWGiZlTtvLUoRHIm3eLuAduinWVpJGLMwb090LQjP9KaV48oXDI7HJJjcKcVtQKpIY24mUlEZvuSo0v7vGzoUoseso35rBOdJKo/VkfAmc44VUlHCVk2i9lJMgK8tHgSFCmcVJg=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=ThL/1M3a; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775826469;\n\tbh=HKLbyRBVfPTHlCYt6B5t9msTPNnxCYsSjPdFZbFLnuw=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=ThL/1M3avfN/caZ2EIVBa9HXiCrGgT28bhLYEM2GPGatVekUgzTZSHrU94ulzFqVw\n\t Hm9PyfMh4G28Mj2bknSQxMfHDT89bxcS4NGCI7hoBBP1MmjR+yr5Ef40s6SFGiuPLN\n\t XsAiqzsaDlfAfrJudlUuHbyOL7t6qSEGq8OXOvp/5CfNJFf9okKC2qNkHRrTuGKqg3\n\t /3iw8LfshG3Z0rFZaHzCk8bjM1wC88SHrqoFqB290VE14Bnu69Hldw/PWT+oZ6Pl9P\n\t aigbfG4oTRGr27uB7JPuGukjvkC0OlHL0MulkD0ByzDyCg0fNh+etelsr3A/idZWFC\n\t zyDUWHbTJSUzQ==", "From": "Nathan Lynch via B4 Relay <devnull+nathan.lynch.amd.com@kernel.org>", "Date": "Fri, 10 Apr 2026 08:07:13 -0500", "Subject": "[PATCH 03/23] dmaengine: sdxi: Add PCI initialization", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260410-sdxi-base-v1-3-1d184cb5c60a@amd.com>", "References": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "In-Reply-To": "<20260410-sdxi-base-v1-0-1d184cb5c60a@amd.com>", "To": "Vinod Koul <vkoul@kernel.org>", "Cc": "Wei Huang <wei.huang2@amd.com>,\n Mario Limonciello <mario.limonciello@amd.com>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Jonathan Cameron <jonathan.cameron@huawei.com>,\n Stephen Bates <Stephen.Bates@amd.com>, PradeepVineshReddy.Kodamati@amd.com,\n John.Kariuki@amd.com, linux-pci@vger.kernel.org,\n linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n Nathan Lynch <nathan.lynch@amd.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775826467; l=7230;\n i=nathan.lynch@amd.com; s=20260410; h=from:subject:message-id;\n bh=3A0BXgIoSercG94OmOdIOrhmik2mZE2IAheGEIhO5Q0=;\n b=2bpWgEy4FtNh9XEmlaLsO4DAUK2nN/Cleb6ZaHIf364SRLwwh+r8I9KiBsaYNRewTH7sMda8a\n ZfFgYojVy55B0AqjxUrkcMD5AgVehdjWknUvWBOpk3qzmtOAnsWHm7Q", "X-Developer-Key": "i=nathan.lynch@amd.com; a=ed25519;\n pk=PK4ozhq+/z9/2Jl5rgDmvHa9raVomv79qM8p1RAFpEw=", "X-Endpoint-Received": "by B4 Relay for nathan.lynch@amd.com/20260410 with\n auth_id=728", "X-Original-From": "Nathan Lynch <nathan.lynch@amd.com>", "Reply-To": "nathan.lynch@amd.com" }, "content": "From: Nathan Lynch <nathan.lynch@amd.com>\n\nAdd enough code to bind a SDXI device via the class code and map its\ncontrol registers and doorbell region. All device resources are\nmanaged with devres at this point, so there is no explicit teardown\npath.\n\nWhile the SDXI specification includes a PCIe binding, the standard is\nintended to be independent of the underlying I/O interconnect. So the\ndriver confines PCI-specific code to pci.c, and the rest (such as\ndevice.c, introduced here) is bus-agnostic. Hence there is some\nindirection: during probe, the bus code registers any matched device\nwith the generic SDXI core, supplying the device and a sdxi_bus_ops\nvector. After the core associates a new sdxi_dev with the device,\nbus-specific initialization proceeds via the sdxi_bus_ops->init()\ncallback.\n\nCo-developed-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Wei Huang <wei.huang2@amd.com>\nSigned-off-by: Nathan Lynch <nathan.lynch@amd.com>\n---\n drivers/dma/Kconfig | 2 ++\n drivers/dma/Makefile | 1 +\n drivers/dma/sdxi/Kconfig | 8 +++++\n drivers/dma/sdxi/Makefile | 6 ++++\n drivers/dma/sdxi/device.c | 26 ++++++++++++++\n drivers/dma/sdxi/pci.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++\n drivers/dma/sdxi/sdxi.h | 45 ++++++++++++++++++++++++\n 7 files changed, 175 insertions(+)", "diff": "diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\nindex e98e3e8c5036..5a19df2da7f2 100644\n--- a/drivers/dma/Kconfig\n+++ b/drivers/dma/Kconfig\n@@ -783,6 +783,8 @@ source \"drivers/dma/fsl-dpaa2-qdma/Kconfig\"\n \n source \"drivers/dma/lgm/Kconfig\"\n \n+source \"drivers/dma/sdxi/Kconfig\"\n+\n source \"drivers/dma/stm32/Kconfig\"\n \n # clients\ndiff --git a/drivers/dma/Makefile b/drivers/dma/Makefile\nindex df566c4958b6..3055ed87bc52 100644\n--- a/drivers/dma/Makefile\n+++ b/drivers/dma/Makefile\n@@ -86,6 +86,7 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o\n obj-$(CONFIG_ST_FDMA) += st_fdma.o\n obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/\n obj-$(CONFIG_INTEL_LDMA) += lgm/\n+obj-$(CONFIG_SDXI) += sdxi/\n \n obj-y += amd/\n obj-y += mediatek/\ndiff --git a/drivers/dma/sdxi/Kconfig b/drivers/dma/sdxi/Kconfig\nnew file mode 100644\nindex 000000000000..a568284cd583\n--- /dev/null\n+++ b/drivers/dma/sdxi/Kconfig\n@@ -0,0 +1,8 @@\n+config SDXI\n+\ttristate \"SDXI support\"\n+\tselect DMA_ENGINE\n+\thelp\n+\t Enable support for Smart Data Accelerator Interface (SDXI)\n+\t Platform Data Mover devices. SDXI is a vendor-neutral\n+\t standard for a memory-to-memory data mover and acceleration\n+\t interface.\ndiff --git a/drivers/dma/sdxi/Makefile b/drivers/dma/sdxi/Makefile\nnew file mode 100644\nindex 000000000000..f84b87d53e27\n--- /dev/null\n+++ b/drivers/dma/sdxi/Makefile\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: GPL-2.0\n+obj-$(CONFIG_SDXI) += sdxi.o\n+\n+sdxi-objs += device.o\n+\n+sdxi-$(CONFIG_PCI_MSI) += pci.o\ndiff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c\nnew file mode 100644\nindex 000000000000..b718ce04afa0\n--- /dev/null\n+++ b/drivers/dma/sdxi/device.c\n@@ -0,0 +1,26 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * SDXI hardware device driver\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#include <linux/device.h>\n+#include <linux/slab.h>\n+\n+#include \"sdxi.h\"\n+\n+int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops)\n+{\n+\tstruct sdxi_dev *sdxi;\n+\n+\tsdxi = devm_kzalloc(dev, sizeof(*sdxi), GFP_KERNEL);\n+\tif (!sdxi)\n+\t\treturn -ENOMEM;\n+\n+\tsdxi->dev = dev;\n+\tsdxi->bus_ops = ops;\n+\tdev_set_drvdata(dev, sdxi);\n+\n+\treturn sdxi->bus_ops->init(sdxi);\n+}\ndiff --git a/drivers/dma/sdxi/pci.c b/drivers/dma/sdxi/pci.c\nnew file mode 100644\nindex 000000000000..f3f8485e50e3\n--- /dev/null\n+++ b/drivers/dma/sdxi/pci.c\n@@ -0,0 +1,87 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * SDXI PCI device code\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#include <linux/dev_printk.h>\n+#include <linux/dma-mapping.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/iomap.h>\n+#include <linux/module.h>\n+#include <linux/pci.h>\n+\n+#include \"sdxi.h\"\n+\n+enum sdxi_mmio_bars {\n+\tSDXI_PCI_BAR_CTL_REGS = 0,\n+\tSDXI_PCI_BAR_DOORBELL = 2,\n+};\n+\n+static struct pci_dev *sdxi_to_pci_dev(const struct sdxi_dev *sdxi)\n+{\n+\treturn to_pci_dev(sdxi_to_dev(sdxi));\n+}\n+\n+static int sdxi_pci_init(struct sdxi_dev *sdxi)\n+{\n+\tstruct pci_dev *pdev = sdxi_to_pci_dev(sdxi);\n+\tstruct device *dev = &pdev->dev;\n+\tint ret;\n+\n+\tret = pcim_enable_device(pdev);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"failed to enable device\\n\");\n+\n+\tret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"failed to set DMA masks\\n\");\n+\n+\tsdxi->ctrl_regs = pcim_iomap_region(pdev, SDXI_PCI_BAR_CTL_REGS,\n+\t\t\t\t\t KBUILD_MODNAME);\n+\tif (IS_ERR(sdxi->ctrl_regs)) {\n+\t\treturn dev_err_probe(dev, PTR_ERR(sdxi->ctrl_regs),\n+\t\t\t\t \"failed to map control registers\\n\");\n+\t}\n+\n+\tsdxi->dbs = pcim_iomap_region(pdev, SDXI_PCI_BAR_DOORBELL,\n+\t\t\t\t KBUILD_MODNAME);\n+\tif (IS_ERR(sdxi->dbs)) {\n+\t\treturn dev_err_probe(dev, PTR_ERR(sdxi->dbs),\n+\t\t\t\t \"failed to map doorbell region\\n\");\n+\t}\n+\n+\tpci_set_master(pdev);\n+\treturn 0;\n+}\n+\n+static const struct sdxi_bus_ops sdxi_pci_ops = {\n+\t.init = sdxi_pci_init,\n+};\n+\n+static int sdxi_pci_probe(struct pci_dev *pdev,\n+\t\t\t const struct pci_device_id *id)\n+{\n+\treturn sdxi_register(&pdev->dev, &sdxi_pci_ops);\n+}\n+\n+static const struct pci_device_id sdxi_id_table[] = {\n+\t{ PCI_DEVICE_CLASS(PCI_CLASS_ACCELERATOR_SDXI, 0xffffff) },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(pci, sdxi_id_table);\n+\n+static struct pci_driver sdxi_driver = {\n+\t.name = \"sdxi\",\n+\t.id_table = sdxi_id_table,\n+\t.probe = sdxi_pci_probe,\n+\t.sriov_configure = pci_sriov_configure_simple,\n+};\n+\n+MODULE_AUTHOR(\"Wei Huang\");\n+MODULE_AUTHOR(\"Nathan Lynch\");\n+MODULE_DESCRIPTION(SDXI_DRV_DESC);\n+MODULE_LICENSE(\"GPL\");\n+module_pci_driver(sdxi_driver);\ndiff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h\nnew file mode 100644\nindex 000000000000..9430f3b8d0b3\n--- /dev/null\n+++ b/drivers/dma/sdxi/sdxi.h\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * SDXI device driver header\n+ *\n+ * Copyright Advanced Micro Devices, Inc.\n+ */\n+\n+#ifndef DMA_SDXI_H\n+#define DMA_SDXI_H\n+\n+#include <linux/compiler_types.h>\n+#include <linux/types.h>\n+\n+#define SDXI_DRV_DESC\t\t\"SDXI driver\"\n+\n+struct sdxi_dev;\n+\n+/**\n+ * struct sdxi_bus_ops - Bus-specific methods for SDXI devices.\n+ */\n+struct sdxi_bus_ops {\n+\t/**\n+\t * @init: Map control registers and doorbell region, allocate\n+\t * IRQ ranges. Invoked before bus-agnostic SDXI\n+\t * function initialization.\n+\t */\n+\tint (*init)(struct sdxi_dev *sdxi);\n+};\n+\n+struct sdxi_dev {\n+\tstruct device *dev;\n+\tvoid __iomem *ctrl_regs;\t/* virt addr of ctrl registers */\n+\tvoid __iomem *dbs;\t\t/* virt addr of doorbells */\n+\n+\tconst struct sdxi_bus_ops *bus_ops;\n+};\n+\n+static inline struct device *sdxi_to_dev(const struct sdxi_dev *sdxi)\n+{\n+\treturn sdxi->dev;\n+}\n+\n+int sdxi_register(struct device *dev, const struct sdxi_bus_ops *ops);\n+\n+#endif /* DMA_SDXI_H */\n", "prefixes": [ "03/23" ] }