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GET /api/1.1/patches/2221597/?format=api
{ "id": 2221597, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221597/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-4-lucaaamaral@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409220614.65558-4-lucaaamaral@gmail.com>", "date": "2026-04-09T22:06:11", "name": "[v6,3/6] target/arm/emulate: add load/store pair", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ebacff1e5fe6aa2b3a0167ccebb16b23f371339a", "submitter": { "id": 92822, "url": "http://patchwork.ozlabs.org/api/1.1/people/92822/?format=api", "name": "Lucas Amaral", "email": "lucaaamaral@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409220614.65558-4-lucaaamaral@gmail.com/mbox/", "series": [ { "id": 499364, "url": "http://patchwork.ozlabs.org/api/1.1/series/499364/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499364", "date": "2026-04-09T22:06:10", "name": "target/arm: ISV=0 data abort emulation library", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499364/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221597/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221597/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Ox19hzQ6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1334;\n envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x1334.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add emulation for load/store pair instructions (DDI 0487 C3.3.14 --\nC3.3.16). All addressing modes are covered: non-temporal (STNP/LDNP),\npost-indexed, signed offset, and pre-indexed.\n\nInstruction coverage:\n - STP/LDP (GPR): 32/64-bit pairs, all addressing modes\n - STP/LDP (SIMD/FP): 32/64/128-bit pairs, all addressing modes\n - LDPSW: sign-extending 32-bit pair load\n - STGP: store allocation tag pair (tag operation is NOP for MMIO)\n\nSigned-off-by: Lucas Amaral <lucaaamaral@gmail.com>\n---\n target/arm/emulate/a64-ldst.decode | 68 ++++++++++++++++++\n target/arm/emulate/arm_emulate.c | 108 +++++++++++++++++++++++++++++\n 2 files changed, 176 insertions(+)", "diff": "diff --git a/target/arm/emulate/a64-ldst.decode b/target/arm/emulate/a64-ldst.decode\nindex af6babe1..f3de3f86 100644\n--- a/target/arm/emulate/a64-ldst.decode\n+++ b/target/arm/emulate/a64-ldst.decode\n@@ -10,6 +10,9 @@\n # 'u' flag: 0 = 9-bit signed immediate (byte offset), 1 = 12-bit unsigned (needs << sz)\n &ldst_imm rt rn imm sz sign w p unpriv ext u\n \n+# Load/store pair (GPR and SIMD/FP)\n+&ldstpair rt2 rt rn imm sz sign w p\n+\n # Load/store register offset\n &ldst rm rn rt sign ext sz opt s\n \n@@ -24,6 +27,9 @@\n # Load/store unsigned offset (12-bit, handler scales by << sz)\n @ldst_uimm .. ... . .. .. imm:12 rn:5 rt:5 &ldst_imm u=1 unpriv=0 p=0 w=0\n \n+# Load/store pair: imm7 is signed, scaled by element size in handler\n+@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair\n+\n # Load/store register offset\n @ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst\n \n@@ -128,6 +134,68 @@ STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=\n LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign=0 ext=0\n LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=0 ext=0 sz=4\n \n+### Load/store pair — non-temporal (STNP/LDNP)\n+\n+# STNP/LDNP: offset only, no writeback. Non-temporal hint ignored.\n+STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+\n+### Load/store pair — post-indexed\n+\n+STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=1 w=1\n+STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=1 w=1\n+STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1\n+LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=1 w=1\n+\n+### Load/store pair — signed offset\n+\n+STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=0\n+STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=0\n+STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=0\n+\n+### Load/store pair — pre-indexed\n+\n+STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=1 p=0 w=1\n+STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=2 sign=0 p=0 w=1\n+STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1\n+LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=4 sign=0 p=0 w=1\n+\n+### Load/store pair — STGP (store allocation tag + pair)\n+\n+STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=1 w=1\n+STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=0\n+STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3 sign=0 p=0 w=1\n+\n ### Load/store register — register offset\n \n # GPR\ndiff --git a/target/arm/emulate/arm_emulate.c b/target/arm/emulate/arm_emulate.c\nindex 79f42d44..2d86b90f 100644\n--- a/target/arm/emulate/arm_emulate.c\n+++ b/target/arm/emulate/arm_emulate.c\n@@ -171,6 +171,114 @@ static uint64_t load_extend(uint64_t val, int sz, int sign, int ext)\n return val;\n }\n \n+/*\n+ * Load/store pair: STP, LDP, STNP, LDNP, STGP, LDPSW\n+ * (DDI 0487 C3.3.14 -- C3.3.16)\n+ */\n+\n+static bool trans_STP(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz; /* 4 or 8 bytes */\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset; /* post-index: unmodified base */\n+ uint8_t buf[16]; /* max 2 x 8 bytes */\n+\n+ mem_st(ctx, buf, esize, gpr_read(ctx, a->rt));\n+ mem_st(ctx, buf + esize, esize, gpr_read(ctx, a->rt2));\n+\n+ if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n+static bool trans_LDP(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz;\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset;\n+ uint8_t buf[16];\n+\n+ if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+ uint64_t v1 = mem_ld(ctx, buf, esize);\n+ uint64_t v2 = mem_ld(ctx, buf + esize, esize);\n+\n+ /* LDPSW: sign-extend 32-bit values to 64-bit (sign=1, sz=2) */\n+ if (a->sign) {\n+ v1 = sextract64(v1, 0, 8 * esize);\n+ v2 = sextract64(v2, 0, 8 * esize);\n+ }\n+\n+ gpr_write(ctx, a->rt, v1);\n+ gpr_write(ctx, a->rt2, v2);\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n+/* STGP: tag operation is a NOP for emulation; data stored via STP */\n+static bool trans_STGP(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ return trans_STP(ctx, a);\n+}\n+\n+/*\n+ * SIMD/FP load/store pair: STP_v, LDP_v\n+ * (DDI 0487 C3.3.14 -- C3.3.16)\n+ */\n+\n+static bool trans_STP_v(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz; /* 4, 8, or 16 bytes */\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset;\n+ uint8_t buf[32]; /* max 2 x 16 bytes */\n+\n+ fpreg_read(ctx, a->rt, buf, esize);\n+ fpreg_read(ctx, a->rt2, buf + esize, esize);\n+\n+ if (mem_write(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n+static bool trans_LDP_v(DisasContext *ctx, arg_ldstpair *a)\n+{\n+ int esize = 1 << a->sz;\n+ int64_t offset = (int64_t)a->imm << a->sz;\n+ uint64_t base = base_read(ctx, a->rn);\n+ uint64_t va = a->p ? base : base + offset;\n+ uint8_t buf[32];\n+\n+ if (mem_read(ctx, va, buf, 2 * esize) != 0) {\n+ return true;\n+ }\n+\n+ fpreg_write(ctx, a->rt, buf, esize);\n+ fpreg_write(ctx, a->rt2, buf + esize, esize);\n+\n+ if (a->w) {\n+ base_write(ctx, a->rn, base + offset);\n+ }\n+ return true;\n+}\n+\n /* Load/store single -- immediate (GPR) (DDI 0487 C3.3.8 -- C3.3.13) */\n \n static bool trans_STR_i(DisasContext *ctx, arg_ldst_imm *a)\n", "prefixes": [ "v6", "3/6" ] }