Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2221559/?format=api
{ "id": 2221559, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221559/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260409190801.1133292-1-avinashd@linux.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260409190801.1133292-1-avinashd@linux.ibm.com>", "date": "2026-04-09T19:08:01", "name": "[v2] rs6000: Add long long support and fix 32 bit failures for __builtin_ppc_atomic_cas_local [PR124800]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c0cbecb30931430bf3a56b55a8fd18aa01b94b0b", "submitter": { "id": 91453, "url": "http://patchwork.ozlabs.org/api/1.1/people/91453/?format=api", "name": "Avinash Jayakar", "email": "avinashd@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260409190801.1133292-1-avinashd@linux.ibm.com/mbox/", "series": [ { "id": 499345, "url": "http://patchwork.ozlabs.org/api/1.1/series/499345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=499345", "date": "2026-04-09T19:08:01", "name": "[v2] rs6000: Add long long support and fix 32 bit failures for __builtin_ppc_atomic_cas_local [PR124800]", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221559/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221559/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=bfHvaS66;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=bfHvaS66", "sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com", "sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com", "server2.sourceware.org;\n arc=none smtp.remote-ip=148.163.158.5" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org [38.145.34.32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fs8bx3DXmz1yHG\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Apr 2026 05:08:44 +1000 (AEST)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 5D0244BA2E0D\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 9 Apr 2026 19:08:42 +0000 (GMT)", "from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n [148.163.158.5])\n by sourceware.org (Postfix) with ESMTPS id DC2744BA2E06;\n Thu, 9 Apr 2026 19:08:10 +0000 (GMT)", "from pps.filterd (m0353725.ppops.net [127.0.0.1])\n by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6399v43u2212474; Thu, 9 Apr 2026 19:08:10 GMT", "from ppma22.wdc07v.mail.ibm.com\n (5c.69.3da9.ip4.static.sl-reverse.com [169.61.105.92])\n by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4dcn2hnrxe-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Thu, 09 Apr 2026 19:08:09 +0000 (GMT)", "from pps.filterd (ppma22.wdc07v.mail.ibm.com [127.0.0.1])\n by ppma22.wdc07v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id\n 639H0GwF007881;\n Thu, 9 Apr 2026 19:08:09 GMT", "from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225])\n by ppma22.wdc07v.mail.ibm.com (PPS) with ESMTPS id 4dcmg2n1pr-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Thu, 09 Apr 2026 19:08:08 +0000", "from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com\n [10.20.54.104])\n by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 639J847345351198\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Thu, 9 Apr 2026 19:08:05 GMT", "from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id D16BC2004B;\n Thu, 9 Apr 2026 19:08:04 +0000 (GMT)", "from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 548F620043;\n Thu, 9 Apr 2026 19:08:02 +0000 (GMT)", "from li-4c4c4544-0036-3810-8050-b5c04f423534.ibm.com.com (unknown\n [9.39.23.103]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP;\n Thu, 9 Apr 2026 19:08:02 +0000 (GMT)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 5D0244BA2E0D", "OpenDKIM Filter v2.11.0 sourceware.org DC2744BA2E06" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org DC2744BA2E06", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org DC2744BA2E06", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1775761691; cv=none;\n b=uRonC0dU44UJV1YVRZmsm1f/5ZJA+bm97xr7eMZtpuZZ/EO4nFgldQlFRXCW2oA6A3ULrdeeFnXiHdFrHfNyUudQuZwkQolSRyKsD5QQ2E/L+bQkz4G55Pt1dTp464+6gqNPAPkhV+jrr9krTjgGEjWiN79k31O/qR8oD9lruRc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1775761691; c=relaxed/simple;\n bh=yOtL4naDOUwdpVofrlCGoTAQW3dTl6qWLrA0UpiqKqo=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=R/xkC2DbWKRMko6Zvx0D+Y4WKOpaaVMnpll9/ZDmq57zpLzWoJtc+HQUNqYgAPbJiktrcJ67wLdQxZIr5Kd4GAM21Plsd+elMTjA10/oK357S/qiNT34C0XrqKR8MWRT/kH5Zqdu/NCvAFJq2fTLx4ZJNuLbvihRy9S4uVMAErQ=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:date:from:message-id:mime-version\n :subject:to; s=pp1; bh=O/bOK5cEEpMCp+jVC17+ZzQfpoKlN0lLp0lGf3LLj\n QQ=; b=bfHvaS66kpCLmyKR5Q+8y4d/NaMmI8jyE1gl/G2W3wzeJVbAozq5BKFNp\n FMsgatBla4pe82kjY+gnPf748mwxicoLChcGVxyyX1rB15AzLzlkpeJ79LmBp2jx\n VEBFBgIb1cWSCvlmDGP5lvM5E8gP9GIRzjAFSuEXYDyJw9rQshmlGR4QANeGRuh6\n dFm0DChwVLvt8KonS9YMD0DgzLPgV2o3JbTWrCUCgstV3mVaYNz0E9JUtSu5cf3r\n n9fqKnzmndrj2NnHO+J9zbpiL+Q6hD+nLAZGPIiO71vlit6LZfSX8MeW8w6Vp3mb\n dNhZGEKgNoKmfn8u7S2Kqsrb8VpzA==", "From": "Avinash Jayakar <avinashd@linux.ibm.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "segher@kernel.crashing.org, jskumari@linux.ibm.com,\n meissner@linux.ibm.com,\n dje.gcc@gmail.com, linkw@gcc.gnu.org, jeevitha@linux.ibm.com,\n kishan@linux.ibm.com, mmatti@linux.ibm.com, vijay@linux.ibm.com", "Subject": "[PATCH v2]rs6000: Add long long support and fix 32 bit failures for\n __builtin_ppc_atomic_cas_local [PR124800]", "Date": "Fri, 10 Apr 2026 00:38:01 +0530", "Message-ID": "<20260409190801.1133292-1-avinashd@linux.ibm.com>", "X-Mailer": "git-send-email 2.51.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-Reinject": "loops=2 maxloops=12", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA5MDE3MiBTYWx0ZWRfX55y5YtsqMCaJ\n 08URrccBEiCtSx0kOPBymOR403KL5nH3Xfsnc3cLReXJdAOxI/pI4+HfZjmw1lW6djSkJONCR2V\n 8TAKXJNqvDJ5Yyi2phpmwNc0/owMziNQ2B/rvO0UDi9KGHxWvAmZ+UTU4B9ol85GEv9IDFEZ47g\n gPqpVSTXAOjNPt63y1TxQrg+DP1p4zJHCCElos744qRbSUy7Tn/QTGVxE6AdolQ6NfyPDy+T1FL\n KojYGp+0s7ubHfWsOJWjr5umncD9P3YIUqjGC+jhFzVsybCDdAz5a7eJ914ineHejmjESx07+dy\n 6y5hAoSjWv7CJ4ilfiGXRFTw/ooWIJs9sgcW1SdLTC1EIe15ZplsZFZKy+DH/7ATLSZRNNklIEn\n 4/XS9boH8q6sd7VQCdcvaO0G/Sl1Gmhh1rDs6OVPGxrOjJivGOClfpxb7eo2KjKToee228SkjQb\n oh4ZbRp3X7icO350tUA==", "X-Proofpoint-GUID": "pWJWrmC_fizpXru7KFmEi7AmfMhKGsC5", "X-Authority-Analysis": "v=2.4 cv=a/wAM0SF c=1 sm=1 tr=0 ts=69d7f919 cx=c_pps\n a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17\n a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22\n a=V8glGbnc2Ofi9Qvn3v5h:22 a=mDV3o1hIAAAA:8 a=VnNF1IyMAAAA:8\n a=vEIiV6tnPpsqkQty818A:9", "X-Proofpoint-ORIG-GUID": "DyKBbGKjSzV2mmh4wXntVl2YkxOQKYaS", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-09_04,2026-04-09_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 priorityscore=1501\n phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090172", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Changes from v1:\n* Use complete source code instead of compact macros in test cases.\n* Use lp64 where __int128 type is needed.\n* Add __int128 overloads.\n\nBootstrapped and regtested on powerpc64-linux-gnu (with -m32 and -m64)\nand powerpc64le-linux-gnu, with no regressions. Ok for trunk?\n\nThanks,\nAvinash Jayakar\n\nA few types were not tested with the patch\nhttps://gcc.gnu.org/pipermail/gcc-patches/2026-March/711326.html\ni.e., (signed/unsigned) long long, and long support in 32 bit system.\nThis patch adds support for long long in 64 bit system and for long in\n32 bit. Also only __int128 type without the 'vector' prefix was missed,\nthis patch adds overloads for it.\n\nAlthough the generic builtin __atomic_compare_exchange does support long\nlong even in 32 bit, it does not generate larx instructions in assembly,\nand instead expands using internal function. Therefore decided not to\nsupport the new builtin for this type in 32 bit.\n\nAdded a few more tests for checking this failure scenario in 32 bit, and\nseparated out 32 bit tests from 64 bit tests.\n\n2026-04-10 Avinash Jayakar <avinashd@linux.ibm.com>\n\ngcc/ChangeLog:\n\tPR target/124800\n\t* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add\n\tlong long support. Expand using SI mode for long type in 32 bit.\n\t* config/rs6000/rs6000-builtins.def: New builtins for long long.\n\t* config/rs6000/rs6000-overload.def: New overloads for long\n\tlong and __int128.\n\ngcc/testsuite/ChangeLog:\n\tPR target/124800\n\t* gcc.target/powerpc/acmp-tst.c: Run only for 64 bit or where\n\t__int128 is supported.\n\t* gcc.target/powerpc/acmp-tst-32-fail.c: New test.\n\t* gcc.target/powerpc/acmp-tst-32.c: New test.\n---\n gcc/config/rs6000/rs6000-builtin.cc | 15 +-\n gcc/config/rs6000/rs6000-builtins.def | 2 +\n gcc/config/rs6000/rs6000-overload.def | 12 +-\n .../gcc.target/powerpc/acmp-tst-32-fail.c | 23 +++\n .../gcc.target/powerpc/acmp-tst-32.c | 73 +++++++++\n gcc/testsuite/gcc.target/powerpc/acmp-tst.c | 147 +++++++++++++++---\n 6 files changed, 242 insertions(+), 30 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c\n create mode 100644 gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c", "diff": "diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc\nindex bbf60de3b1b..845dd4c1e50 100644\n--- a/gcc/config/rs6000/rs6000-builtin.cc\n+++ b/gcc/config/rs6000/rs6000-builtin.cc\n@@ -3288,7 +3288,8 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,\n || fcode == RS6000_BIF_PPC_ATOMIC_CAS_HI\n || fcode == RS6000_BIF_PPC_ATOMIC_CAS_SI\n || fcode == RS6000_BIF_PPC_ATOMIC_CAS_DI\n- || fcode == RS6000_BIF_PPC_ATOMIC_CAS_TI)\n+ || fcode == RS6000_BIF_PPC_ATOMIC_CAS_TI\n+ || fcode == RS6000_BIF_PPC_ATOMIC_CAS_DI_LL)\n {\n machine_mode mode; // Get mode based on BIF ID (QImode, SImode, etc.)\n \n@@ -3307,13 +3308,21 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,\n \t icode = CODE_FOR_atomic_compare_and_swap_localsi;\n \t break;\n \tcase RS6000_BIF_PPC_ATOMIC_CAS_DI:\n-\t mode = DImode;\n-\t icode = CODE_FOR_atomic_compare_and_swap_localdi;\n+\t mode = TARGET_32BIT ? SImode : DImode;\n+\t icode = TARGET_32BIT ? CODE_FOR_atomic_compare_and_swap_localsi\n+\t\t\t : CODE_FOR_atomic_compare_and_swap_localdi;\n \t break;\n \tcase RS6000_BIF_PPC_ATOMIC_CAS_TI:\n \t mode = TImode;\n \t icode = CODE_FOR_atomic_compare_and_swap_localti;\n \t break;\n+\tcase RS6000_BIF_PPC_ATOMIC_CAS_DI_LL:\n+\t if (TARGET_32BIT)\n+\t error (\"Invalid arguments to %qs\",\n+\t\t \"__builtin_ppc_atomic_cas_local\");\n+\t mode = DImode;\n+\t icode = CODE_FOR_atomic_compare_and_swap_localdi;\n+\t break;\n \tdefault:\n \t gcc_unreachable ();\n \t}\ndiff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def\nindex 577c9d6c8f0..a7918b4184d 100644\n--- a/gcc/config/rs6000/rs6000-builtins.def\n+++ b/gcc/config/rs6000/rs6000-builtins.def\n@@ -255,6 +255,8 @@\n PPC_ATOMIC_CAS_SI nothing {}\n bool __builtin_ppc_atomic_cas_local_di (long *, long *, long *, const int, const int, const int);\n PPC_ATOMIC_CAS_DI nothing {}\n+ bool __builtin_ppc_atomic_cas_local_di_ll (long long *, long long *, long long *, const int, const int, const int);\n+ PPC_ATOMIC_CAS_DI_LL nothing {}\n bool __builtin_ppc_atomic_cas_local_ti (vsq *, vsq *, vsq *, const int, const int, const int);\n PPC_ATOMIC_CAS_TI nothing {}\n \ndiff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def\nindex 8f2fa978475..d2b1feadb6a 100644\n--- a/gcc/config/rs6000/rs6000-overload.def\n+++ b/gcc/config/rs6000/rs6000-overload.def\n@@ -96,10 +96,18 @@\n PPC_ATOMIC_CAS_DI PPC_ATOMIC_CAS_SDI\n bool __builtin_ppc_atomic_cas_local (unsigned long *, unsigned long *, unsigned long *, const int, const int, const int);\n PPC_ATOMIC_CAS_DI PPC_ATOMIC_CAS_UDI\n- bool __builtin_ppc_atomic_cas_local (vsq *, vsq *, vsq *, const int, const int, const int);\n+ bool __builtin_ppc_atomic_cas_local (signed long long *, signed long long *, signed long long *, const int, const int, const int);\n+ PPC_ATOMIC_CAS_DI_LL PPC_ATOMIC_CAS_SDI_LL\n+ bool __builtin_ppc_atomic_cas_local (unsigned long long *, unsigned long long *, unsigned long long *, const int, const int, const int);\n+ PPC_ATOMIC_CAS_DI_LL PPC_ATOMIC_CAS_UDI_LL\n+ bool __builtin_ppc_atomic_cas_local (signed __int128 *, signed __int128 *, signed __int128 *, const int, const int, const int);\n PPC_ATOMIC_CAS_TI PPC_ATOMIC_CAS_STI\n- bool __builtin_ppc_atomic_cas_local (vuq *, vuq *, vuq *, const int, const int, const int);\n+ bool __builtin_ppc_atomic_cas_local (unsigned __int128 *, unsigned __int128 *, unsigned __int128 *, const int, const int, const int);\n PPC_ATOMIC_CAS_TI PPC_ATOMIC_CAS_UTI\n+ bool __builtin_ppc_atomic_cas_local (vsq *, vsq *, vsq *, const int, const int, const int);\n+ PPC_ATOMIC_CAS_TI PPC_ATOMIC_CAS_VSTI\n+ bool __builtin_ppc_atomic_cas_local (vuq *, vuq *, vuq *, const int, const int, const int);\n+ PPC_ATOMIC_CAS_TI PPC_ATOMIC_CAS_VUTI\n \n [BCDADD, __builtin_bcdadd, __builtin_vec_bcdadd]\n vsq __builtin_vec_bcdadd (vsq, vsq, const int);\ndiff --git a/gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c\nnew file mode 100644\nindex 00000000000..07a327baf9c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c\n@@ -0,0 +1,23 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target ilp32 } */\n+/* { dg-options \"-O2 -m32\" } */\n+\n+bool word_exchange_di2 (long long *ptr, long long *expected, long long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_sdi2 (signed long long *ptr, signed long long *expected, signed long long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_udi2 (unsigned long long *ptr, unsigned long long *expected, unsigned long long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+/* { dg-excess-errors \"This test is expected to fail on 32-bit\" } */\ndiff --git a/gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c\nnew file mode 100644\nindex 00000000000..2de2972a381\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c\n@@ -0,0 +1,73 @@\n+/* { dg-do compile } */\n+/* { dg-require-effective-target ilp32 } */\n+/* { dg-options \"-O2 -m32\" } */\n+\n+bool word_exchange_qi (signed char *ptr, signed char *expected, signed char * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_uqi (unsigned char *ptr, unsigned char *expected, unsigned char * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_hi (short *ptr, short *expected, short * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_shi (signed short *ptr, signed short *expected, signed short * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_uhi (unsigned short *ptr, unsigned short *expected, unsigned short * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_si (int *ptr, int *expected, int * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_ssi (signed int *ptr, signed int *expected, signed int * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_usi (unsigned int *ptr, unsigned int *expected, unsigned int * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_di (long *ptr, long *expected, long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_sdi (signed long *ptr, signed long *expected, signed long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_udi (unsigned long *ptr, unsigned long *expected, unsigned long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */\n+/* { dg-final { scan-assembler-times {\\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */\n+/* { dg-final { scan-assembler-times {\\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */\ndiff --git a/gcc/testsuite/gcc.target/powerpc/acmp-tst.c b/gcc/testsuite/gcc.target/powerpc/acmp-tst.c\nindex 6ebd2ebbc28..6f0f8518b49 100644\n--- a/gcc/testsuite/gcc.target/powerpc/acmp-tst.c\n+++ b/gcc/testsuite/gcc.target/powerpc/acmp-tst.c\n@@ -1,32 +1,129 @@\n /* { dg-do compile } */\n+/* { dg-require-effective-target lp64 } */\n /* { dg-options \"-O2\" } */\n \n-#define TESTS \\\n- X(signed char, qi) \\\n- X(unsigned char, uqi) \\\n- X(short, hi) \\\n- X(signed short, shi) \\\n- X(unsigned short, uhi) \\\n- X(int, si) \\\n- X(signed int, ssi) \\\n- X(unsigned int, usi) \\\n- X(long, di) \\\n- X(signed long, sdi) \\\n- X(unsigned long, udi) \\\n- X(vector signed __int128, sti) \\\n- X(vector unsigned __int128, uti)\n-\n-#define X(T, name) \\\n-bool word_exchange_##name (T *ptr, T *expected, T * desired) \\\n-{ \\\n- return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0, \\\n-\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); \\\n-}\n-\n-TESTS\n+bool word_exchange_sqi (signed char *ptr, signed char *expected, signed char * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_uqi (unsigned char *ptr, unsigned char *expected, unsigned char * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_hi (short *ptr, short *expected, short * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_shi (signed short *ptr, signed short *expected, signed short * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_uhi (unsigned short *ptr, unsigned short *expected, unsigned short * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_si (int *ptr, int *expected, int * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_ssi (signed int *ptr, signed int *expected, signed int * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_usi (unsigned int *ptr, unsigned int *expected, unsigned int * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_di (long *ptr, long *expected, long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_sdi (signed long *ptr, signed long *expected, signed long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_udi (unsigned long *ptr, unsigned long *expected, unsigned long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_di2 (long long *ptr, long long *expected, long long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_sdi2 (signed long long *ptr, signed long long *expected, signed long long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_udi2 (unsigned long long *ptr, unsigned long long *expected, unsigned long long * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_ti (__int128 *ptr, __int128 *expected, __int128 * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_sti (signed __int128 *ptr, signed __int128 *expected, signed __int128 * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_uti (unsigned __int128 *ptr, unsigned __int128 *expected, unsigned __int128 * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_vti (vector __int128 *ptr, vector __int128 *expected, vector __int128 * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_vsti (vector signed __int128 *ptr, vector signed __int128 *expected, vector signed __int128 * desired)\n+{\n+ return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n+\n+bool word_exchange_vuti (vector unsigned __int128 *ptr, vector unsigned __int128 *expected, vector unsigned __int128 * desired)\n+{\n+return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,\n+\t\t\t\t __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);\n+}\n \n /* { dg-final { scan-assembler-times {\\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */\n /* { dg-final { scan-assembler-times {\\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */\n /* { dg-final { scan-assembler-times {\\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */\n-/* { dg-final { scan-assembler-times {\\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */\n-/* { dg-final { scan-assembler-times {\\mlqarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */\n+/* { dg-final { scan-assembler-times {\\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */\n+/* { dg-final { scan-assembler-times {\\mlqarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */\n", "prefixes": [ "v2" ] }