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GET /api/1.1/patches/2221535/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2221535,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221535/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com>",
    "date": "2026-04-09T16:37:36",
    "name": "pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "aece7d9302e90777811e1f60f8cf76eba88cc0b4",
    "submitter": {
        "id": 9539,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/9539/?format=api",
        "name": "Lad, Prabhakar",
        "email": "prabhakar.csengg@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/",
    "series": [
        {
            "id": 499329,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/499329/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499329",
            "date": "2026-04-09T16:37:36",
            "name": "pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/499329/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2221535/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2221535/checks/",
    "tags": {},
    "headers": {
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        "From": "Prabhakar <prabhakar.csengg@gmail.com>",
        "X-Google-Original-From": "Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>",
        "To": "Geert Uytterhoeven <geert+renesas@glider.be>,\n\tLinus Walleij <linusw@kernel.org>",
        "Cc": "linux-renesas-soc@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tPrabhakar <prabhakar.csengg@gmail.com>,\n\tBiju Das <biju.das.jz@bp.renesas.com>,\n\tFabrizio Castro <fabrizio.castro.jz@renesas.com>,\n\tLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>",
        "Subject": "[PATCH] pinctrl: renesas: rzg2l: Add SR register cache for PM\n suspend/resume",
        "Date": "Thu,  9 Apr 2026 17:37:36 +0100",
        "Message-ID": "<20260409163736.2419396-1-prabhakar.mahadev-lad.rj@bp.renesas.com>",
        "X-Mailer": "git-send-email 2.53.0",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-gpio@vger.kernel.org",
        "List-Id": "<linux-gpio.vger.kernel.org>",
        "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>",
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        "MIME-Version": "1.0",
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    },
    "content": "From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n\nInclude the SR (Slew Rate) register in the PM suspend/resume register\ncache.\n\nSigned-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 +++++++++++-\n 1 file changed, 11 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex 561e6018fd89..347926dad0c9 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -322,6 +322,7 @@ struct rzg2l_pinctrl_pin_settings {\n  * @pupd: PUPD registers cache\n  * @ien: IEN registers cache\n  * @smt: SMT registers cache\n+ * @sr: SR registers cache\n  * @sd_ch: SD_CH registers cache\n  * @eth_poc: ET_POC registers cache\n  * @oen: Output Enable register cache\n@@ -336,6 +337,7 @@ struct rzg2l_pinctrl_reg_cache {\n \tu32\t*ien[2];\n \tu32\t*pupd[2];\n \tu32\t*smt;\n+\tu32\t*sr;\n \tu8\tsd_ch[2];\n \tu8\teth_poc[2];\n \tu8\toen;\n@@ -2741,6 +2743,10 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)\n \tif (!cache->smt)\n \t\treturn -ENOMEM;\n \n+\tcache->sr = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->sr), GFP_KERNEL);\n+\tif (!cache->sr)\n+\t\treturn -ENOMEM;\n+\n \tfor (u8 i = 0; i < 2; i++) {\n \t\tu32 n_dedicated_pins = pctrl->data->n_dedicated_pins;\n \n@@ -3002,7 +3008,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \tstruct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;\n \n \tfor (u32 port = 0; port < nports; port++) {\n-\t\tbool has_iolh, has_ien, has_pupd, has_smt;\n+\t\tbool has_iolh, has_ien, has_pupd, has_smt, has_sr;\n \t\tu32 off, caps;\n \t\tu8 pincnt;\n \t\tu64 cfg;\n@@ -3023,6 +3029,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \t\thas_ien = !!(caps & PIN_CFG_IEN);\n \t\thas_pupd = !!(caps & PIN_CFG_PUPD);\n \t\thas_smt = !!(caps & PIN_CFG_SMT);\n+\t\thas_sr = !!(caps & PIN_CFG_SR);\n \n \t\tif (suspend)\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);\n@@ -3068,6 +3075,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen\n \n \t\tif (has_smt)\n \t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[port]);\n+\n+\t\tif (has_sr)\n+\t\t\tRZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SR(off), cache->sr[port]);\n \t}\n }\n \n",
    "prefixes": []
}