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GET /api/1.1/patches/2221217/?format=api
{ "id": 2221217, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408042149.1902796-2-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408042149.1902796-2-brian.cain@oss.qualcomm.com>", "date": "2026-04-08T04:21:40", "name": "[v4,1/9] hw/hexagon: Add globalreg model", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7a2003fbf68cfcb83872df7f827f3d1b78379add", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/1.1/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408042149.1902796-2-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 499184, "url": "http://patchwork.ozlabs.org/api/1.1/series/499184/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499184", "date": "2026-04-08T04:21:47", "name": "Hexagon system emulation - Part 3/3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499184/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221217/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221217/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=UGXV7Gzn;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=bS83ycVo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Some of the system registers are shared among all threads\nin the core. This object contains the representation and\ninterface to the system registers.\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n include/hw/hexagon/hexagon_globalreg.h | 56 ++++++\n hw/hexagon/hexagon_globalreg.c | 245 +++++++++++++++++++++++++\n 2 files changed, 301 insertions(+)\n create mode 100644 include/hw/hexagon/hexagon_globalreg.h\n create mode 100644 hw/hexagon/hexagon_globalreg.c", "diff": "diff --git a/include/hw/hexagon/hexagon_globalreg.h b/include/hw/hexagon/hexagon_globalreg.h\nnew file mode 100644\nindex 00000000000..c9e72f30b0a\n--- /dev/null\n+++ b/include/hw/hexagon/hexagon_globalreg.h\n@@ -0,0 +1,56 @@\n+/*\n+ * Hexagon Global Registers QOM Object\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXAGON_GLOBALREG_H\n+#define HEXAGON_GLOBALREG_H\n+\n+#include \"hw/core/qdev.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"qom/object.h\"\n+#include \"target/hexagon/cpu.h\"\n+\n+#define TYPE_HEXAGON_GLOBALREG \"hexagon-globalreg\"\n+OBJECT_DECLARE_SIMPLE_TYPE(HexagonGlobalRegState, HEXAGON_GLOBALREG)\n+\n+struct HexagonGlobalRegState {\n+ SysBusDevice parent_obj;\n+\n+ /* Array of system registers */\n+ uint32_t regs[NUM_SREGS];\n+\n+ /* Global performance cycle counter base */\n+ uint64_t g_pcycle_base;\n+\n+ /* Properties for global register reset values */\n+ uint32_t boot_evb; /* Boot Exception Vector Base (HEX_SREG_EVB) */\n+ uint64_t config_table_addr; /* Configuration table base */\n+ uint32_t dsp_rev; /* DSP revision register (HEX_SREG_REV) */\n+\n+ /* ISDB properties */\n+ bool isdben_etm_enable; /* ISDB ETM enable bit */\n+ bool isdben_dfd_enable; /* ISDB DFD enable bit */\n+ bool isdben_trusted; /* ISDB trusted mode bit */\n+ bool isdben_secure; /* ISDB secure mode bit */\n+};\n+\n+/* Public interface functions */\n+uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t htid);\n+void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t value, uint32_t htid);\n+uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t value);\n+void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t value);\n+void hexagon_globalreg_reset(HexagonGlobalRegState *s);\n+\n+/* Global performance cycle counter access */\n+uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s);\n+void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s,\n+ uint64_t value);\n+\n+#endif /* HEXAGON_GLOBALREG_H */\ndiff --git a/hw/hexagon/hexagon_globalreg.c b/hw/hexagon/hexagon_globalreg.c\nnew file mode 100644\nindex 00000000000..634d3b169fd\n--- /dev/null\n+++ b/hw/hexagon/hexagon_globalreg.c\n@@ -0,0 +1,245 @@\n+/*\n+ * Hexagon Global Registers\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/hexagon/hexagon.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"hw/core/resettable.h\"\n+#include \"migration/vmstate.h\"\n+#include \"qom/object.h\"\n+#include \"target/hexagon/cpu.h\"\n+#include \"target/hexagon/hex_regs.h\"\n+#include \"qemu/log.h\"\n+#include \"qapi/error.h\"\n+\n+#define IMMUTABLE (~0)\n+#define INVALID_REG_VAL 0xdeadbeef\n+\n+/* Global system register mutability masks */\n+static const uint32_t global_sreg_immut_masks[NUM_SREGS] = {\n+ [HEX_SREG_EVB] = 0x000000ff,\n+ [HEX_SREG_MODECTL] = IMMUTABLE,\n+ [HEX_SREG_SYSCFG] = 0x80001c00,\n+ [HEX_SREG_IPENDAD] = IMMUTABLE,\n+ [HEX_SREG_VID] = 0xfc00fc00,\n+ [HEX_SREG_VID1] = 0xfc00fc00,\n+ [HEX_SREG_BESTWAIT] = 0xfffffe00,\n+ [HEX_SREG_IAHL] = 0x00000000,\n+ [HEX_SREG_SCHEDCFG] = 0xfffffee0,\n+ [HEX_SREG_CFGBASE] = IMMUTABLE,\n+ [HEX_SREG_DIAG] = 0x00000000,\n+ [HEX_SREG_REV] = IMMUTABLE,\n+ [HEX_SREG_ISDBST] = IMMUTABLE,\n+ [HEX_SREG_ISDBCFG0] = 0xe0000000,\n+ [HEX_SREG_BRKPTPC0] = 0x00000003,\n+ [HEX_SREG_BRKPTCFG0] = 0xfc007000,\n+ [HEX_SREG_BRKPTPC1] = 0x00000003,\n+ [HEX_SREG_BRKPTCFG1] = 0xfc007000,\n+ [HEX_SREG_ISDBMBXIN] = IMMUTABLE,\n+ [HEX_SREG_ISDBMBXOUT] = 0x00000000,\n+ [HEX_SREG_ISDBEN] = 0xfffffffe,\n+ [HEX_SREG_TIMERLO] = IMMUTABLE,\n+ [HEX_SREG_TIMERHI] = IMMUTABLE,\n+};\n+\n+static void hexagon_globalreg_init(Object *obj)\n+{\n+ HexagonGlobalRegState *s = HEXAGON_GLOBALREG(obj);\n+\n+ memset(s->regs, 0, sizeof(uint32_t) * NUM_SREGS);\n+}\n+\n+static inline uint32_t apply_write_mask(uint32_t new_val, uint32_t cur_val,\n+ uint32_t reg_mask)\n+{\n+ if (reg_mask) {\n+ return (new_val & ~reg_mask) | (cur_val & reg_mask);\n+ }\n+ return new_val;\n+}\n+\n+uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t htid)\n+{\n+ uint32_t value;\n+\n+ g_assert(reg < NUM_SREGS);\n+ g_assert(reg >= HEX_SREG_GLB_START);\n+ g_assert(s);\n+\n+ value = s->regs[reg];\n+\n+ return value;\n+}\n+\n+void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t value, uint32_t htid)\n+{\n+ g_assert(s);\n+ g_assert(reg < NUM_SREGS);\n+ g_assert(reg >= HEX_SREG_GLB_START);\n+ s->regs[reg] = value;\n+}\n+\n+uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t value)\n+{\n+ uint32_t reg_mask;\n+\n+ g_assert(s);\n+ g_assert(reg < NUM_SREGS);\n+ g_assert(reg >= HEX_SREG_GLB_START);\n+ reg_mask = global_sreg_immut_masks[reg];\n+ return reg_mask == IMMUTABLE ?\n+ s->regs[reg] :\n+ apply_write_mask(value, s->regs[reg], reg_mask);\n+}\n+\n+void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg,\n+ uint32_t value)\n+{\n+ g_assert(s);\n+ s->regs[reg] = hexagon_globalreg_masked_value(s, reg, value);\n+}\n+\n+uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s)\n+{\n+ g_assert(s);\n+ return s->g_pcycle_base;\n+}\n+\n+void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s,\n+ uint64_t value)\n+{\n+ g_assert(s);\n+ s->g_pcycle_base = value;\n+}\n+\n+static void do_hexagon_globalreg_reset(HexagonGlobalRegState *s)\n+{\n+ uint32_t isdben_val = 0;\n+\n+ g_assert(s);\n+ memset(s->regs, 0, sizeof(uint32_t) * NUM_SREGS);\n+\n+ s->g_pcycle_base = 0;\n+\n+ s->regs[HEX_SREG_EVB] = s->boot_evb;\n+ s->regs[HEX_SREG_CFGBASE] = HEXAGON_CFG_ADDR_BASE(s->config_table_addr);\n+ s->regs[HEX_SREG_REV] = s->dsp_rev;\n+\n+ if (s->isdben_etm_enable) {\n+ isdben_val |= (1 << 0); /* ETM enable bit */\n+ }\n+ if (s->isdben_dfd_enable) {\n+ isdben_val |= (1 << 1); /* DFD enable bit */\n+ }\n+ if (s->isdben_trusted) {\n+ isdben_val |= (1 << 2); /* Trusted bit */\n+ }\n+ if (s->isdben_secure) {\n+ isdben_val |= (1 << 3); /* Secure bit */\n+ }\n+ s->regs[HEX_SREG_ISDBEN] = isdben_val;\n+ s->regs[HEX_SREG_MODECTL] = 0x1;\n+\n+ /*\n+ * These register indices are placeholders in these arrays\n+ * and their actual values are synthesized from state elsewhere.\n+ * We can initialize these with invalid values so that if we\n+ * mistakenly generate reads, they will look obviously wrong.\n+ */\n+ s->regs[HEX_SREG_PCYCLELO] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PCYCLEHI] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_TIMERLO] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_TIMERHI] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT0] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT1] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT2] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT3] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT4] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT5] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT6] = INVALID_REG_VAL;\n+ s->regs[HEX_SREG_PMUCNT7] = INVALID_REG_VAL;\n+}\n+\n+static void hexagon_globalreg_realize(DeviceState *dev, Error **errp)\n+{\n+}\n+\n+void hexagon_globalreg_reset(HexagonGlobalRegState *s)\n+{\n+ do_hexagon_globalreg_reset(s);\n+}\n+\n+static void hexagon_globalreg_reset_hold(Object *obj, ResetType type)\n+{\n+ HexagonGlobalRegState *s = HEXAGON_GLOBALREG(obj);\n+ do_hexagon_globalreg_reset(s);\n+}\n+\n+static const VMStateDescription vmstate_hexagon_globalreg = {\n+ .name = \"hexagon_globalreg\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (const VMStateField[]){\n+ VMSTATE_UINT32_ARRAY(regs, HexagonGlobalRegState, NUM_SREGS),\n+ VMSTATE_UINT64(g_pcycle_base, HexagonGlobalRegState),\n+ VMSTATE_UINT32(boot_evb, HexagonGlobalRegState),\n+ VMSTATE_UINT64(config_table_addr, HexagonGlobalRegState),\n+ VMSTATE_UINT32(dsp_rev, HexagonGlobalRegState),\n+ VMSTATE_BOOL(isdben_etm_enable, HexagonGlobalRegState),\n+ VMSTATE_BOOL(isdben_dfd_enable, HexagonGlobalRegState),\n+ VMSTATE_BOOL(isdben_trusted, HexagonGlobalRegState),\n+ VMSTATE_BOOL(isdben_secure, HexagonGlobalRegState),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static const Property hexagon_globalreg_properties[] = {\n+ DEFINE_PROP_UINT32(\"boot-evb\", HexagonGlobalRegState, boot_evb, 0x0),\n+ DEFINE_PROP_UINT64(\"config-table-addr\", HexagonGlobalRegState,\n+ config_table_addr, 0xffffffffULL),\n+ DEFINE_PROP_UINT32(\"dsp-rev\", HexagonGlobalRegState, dsp_rev, 0),\n+ DEFINE_PROP_BOOL(\"isdben-etm-enable\", HexagonGlobalRegState,\n+ isdben_etm_enable, false),\n+ DEFINE_PROP_BOOL(\"isdben-dfd-enable\", HexagonGlobalRegState,\n+ isdben_dfd_enable, false),\n+ DEFINE_PROP_BOOL(\"isdben-trusted\", HexagonGlobalRegState,\n+ isdben_trusted, false),\n+ DEFINE_PROP_BOOL(\"isdben-secure\", HexagonGlobalRegState,\n+ isdben_secure, false),\n+};\n+\n+static void hexagon_globalreg_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n+\n+ dc->realize = hexagon_globalreg_realize;\n+ rc->phases.hold = hexagon_globalreg_reset_hold;\n+ dc->vmsd = &vmstate_hexagon_globalreg;\n+ dc->user_creatable = false;\n+ device_class_set_props(dc, hexagon_globalreg_properties);\n+}\n+\n+static const TypeInfo hexagon_globalreg_info = {\n+ .name = TYPE_HEXAGON_GLOBALREG,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(HexagonGlobalRegState),\n+ .instance_init = hexagon_globalreg_init,\n+ .class_init = hexagon_globalreg_class_init,\n+};\n+\n+static void hexagon_globalreg_register_types(void)\n+{\n+ type_register_static(&hexagon_globalreg_info);\n+}\n+\n+type_init(hexagon_globalreg_register_types)\n", "prefixes": [ "v4", "1/9" ] }